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ISM303DAC bảng dữ liệu(PDF) 55 Page - STMicroelectronics

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Giải thích chi tiết về linh kiện  High-performance, low-power, compact 3D accelerometer and 3D magnetometer module
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ISM303DAC bảng dữ liệu(HTML) 55 Page - STMicroelectronics

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ISM303DAC
Register description
80
Table 35. ODR register setting: high resolution (HR) and high frequencies (HF)
The BDU bit is used to inhibit the update of the output registers until both upper and lower
register parts are read. In default mode (BDU = ‘0’) the output register values are updated
continuously. When the BDU is activated (BDU = ‘1’), the content of the output registers is
not updated until both MSB and LSB are read which avoids reading values related to
different sample times.
1011
-
50
10
LP
1100
-
100
10
LP
1101
-
200
10
LP
1110
-
400
10
LP
1111
-
800
10
LP
ODR[3:0]
HF_ODR
ODR selection [Hz]
Bit resolution
Mode
0001
-
12.5
14
HR
0010
-
25
14
HR
0011
-
50
14
HR
0100
-
100
14
HR
0101
0
200
14
HR
0110
0
400
14
HR
0111
0
800
14
HR
0101
1
1600
12
HF
0110
1
3200
12
HF
0111
1
6400
12
HF
Table 34. ODR register setting: power down (PD) and low power (LP) (continued)
ODR[3:0]
HF_ODR
ODR selection [Hz]
Bit resolution
Mode



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