ISM303DAC datasheet(44/80 Pages) STMICROELECTRONICS

44 / 80 page

Digital interfaces

ISM303DAC

44/80

DocID030988 Rev 2

6.1.1

I2C operation

The transaction on the bus is started through a START (ST) signal. A START condition is

defined as a high-to-low transition on the data line while the SCL line is held high. After this

has been transmitted by the master, the bus is considered busy. The next byte of data

transmitted after the start condition contains the address of the slave in the first 7 bits and

the eighth bit tells whether the master is receiving data from the slave or transmitting data to

the slave. When an address is sent, each device in the system compares the first seven bits

after a start condition with its address. If they match, the device considers itself addressed

by the master.

Data transfer with acknowledge is mandatory. The transmitter must release the SDA line

during the acknowledge pulse. The receiver must then pull the data line LOW so that it

remains stable low during the high period of the acknowledge clock pulse. A receiver which

has been addressed is obliged to generate an acknowledge after each byte of data

received.

The I2C embedded inside the magnetometer block of the ISM303DAC behaves like a slave

device and the following protocol must be adhered to. After the start condition (ST) a slave

address is sent, once a slave acknowledge (SAK) has been returned, an 8-bit sub-address

(SUB) is transmitted: the 7 LSb represent the actual register address.

The I2C embedded inside the accelerometer block of the ISM303DAC behaves like a slave

device and the following protocol must be adhered to. After the start condition (ST) a slave

address is sent. Once a slave acknowledge (SAK) has been returned, an 8-bit sub-address

(SUB) is transmitted: the 7 LSb represent the actual register address while the IF_ADD_INC

bit in CTRL2_A (21h) defines the increase in the address.

The slave address is completed with a Read/Write bit. If the bit was ‘1’ (Read), a repeated

START (SR) condition must be issued after the two sub-address bytes; if the bit is ‘0’ (Write)

the master will transmit to the slave with direction unchanged. Table 26 explains how the

SAD+read/write bit pattern is composed, listing all the possible configurations.

Table 22. Transfer when master is writing one byte to slave

Master

SAD + W

SUB

DATA

Slave

SAK

Table 23. Transfer when master is writing multiple bytes to slave

Master

SAD + W

SUB

DATA

Slave

SAK

Table 24. Transfer when master is receiving (reading) one byte of data from slave

Master

SAD + W

SUB

SAD + R

NMAK

Slave

SAK

DATA

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