EKTF6708 datasheet(74/158 Pages) EMC

74 / 158 page

eKTF6708

8-Bit Microcontroller



IC Product Specification (V1.2) 03.12.2020

(This specification is subject to change without prior notice)

6.2 TCC/WDT and Prescaler

Two 8-bit counters are available as prescalers for the TCC and WDT. The TPSR0~ TPSR2

bits of the TCCCR register (Bank 0 R22) are used to determine the ratio of the TCC

prescaler. Likewise, the WPSR0~WPSR2 bits of the WDTCR register (Section 6.1.28

Bank 0 R21) are used to determine the WDT prescaler. The prescaler counter is cleared

by the instructions each time they are written into TCC. The WDT and prescaler are

cleared by the “WDTC” and “SLEP” instructions. Figure 6-3 below depicts the circuit

diagram of TCC/WDT.

The TCCD (Section 6.1.27 TCC Data Register) is an 8-bit timer/counter. The TCC clock

source is from the internal clock only and TCC will be incremented by 1 at Fc clock (without

prescaler). The TCC will stop running when Sleep mode occurs.

The Watchdog Timer is a free running on-chip RC oscillator. The WDT will keep on running

even after the oscillator driver has been turned off (i.e., in Sleep mode). During Normal

operation or Sleep mode, a WDT time-out (if enabled) will cause the device to reset. The

WDT can be enabled or disabled any time during Normal mode by software programming

(see WDTE bit of WDTCR (Section 6.1.28Bank 0 R21) register). With no prescaler, the

WDT time-out period is approximately 18 ms1 (one oscillator start-up timer period).

8 Bit Counter

8 to 1 MUX

Prescaler

TCC(R23)

TCC overflow

interrupt

Data Bus

TPSR2~ TPSR0

(R22)

8 Bit Counter

8 to 1 MUX

Prescaler

WPSR2~ WPSR0

(R21)

WDT

WDTE(R21)

WDT time out

Figure 6-3 TCC and WDT Block Diagram

VDD=5V, WDT time-out period = 16.5ms ± 8%.

VDD=3V, WDT time-out period = 18ms ± 8%.

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