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CS47L24 bảng dữ liệu(PDF) 74 Page - Cirrus Logic

tên linh kiện CS47L24
Giải thích chi tiết về linh kiện  Low Power Audio Hub for Wearable Technology
PDF  256 Pages
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nhà sản xuất  CIRRUS [Cirrus Logic]
Trang chủ  http://www.cirrus.com
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CS47L24 bảng dữ liệu(HTML) 74 Page - Cirrus Logic

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CS47L24
74
Rev 4.1
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R33
(0021h)
Tone
Generator
2
15:0
TONE1_LVL
[23:8]
1000h
Tone Generator 1 DC output level
TONE1_LVL [23:8] is coded as 2’s
complement. Bits [23:20] contain the
integer portion; bits [19:0] contain the
fractional portion.
The digital core 0dBFS level corresponds
to 1000_00h (+1) or F000_00h (-1).
R34
(0022h)
Tone
Generator
3
7:0
TONE1_LVL [7:0]
00h
Tone Generator 1 DC output level
TONE1_LVL [23:8] is coded as 2’s
complement. Bits [23:20] contain the
integer portion; bits [19:0] contain the
fractional portion.
The digital core 0dBFS level corresponds
to 1000_00h (+1) or F000_00h (-1).
R35
(0023h)
Tone
Generator
4
15:0
TONE2_LVL
[23:8]
1000h
Tone Generator 2 DC output level
TONE2_LVL [23:8] is coded as 2’s
complement. Bits [23:20] contain the
integer portion; bits [19:0] contain the
fractional portion.
The digital core 0dBFS level corresponds
to 1000_00h (+1) or F000_00h (-1).
R36
(0024h)
Tone
Generator
5
7:0
TONE2_LVL [7:0]
00h
Tone Generator 2 DC output level
TONE2_LVL
[23:8] is coded as 2’s
complement. Bits [23:20] contain the
integer portion; bits [19:0] contain the
fractional portion.
The digital core 0dBFS level corresponds
to 1000_00h (+1) or F000_00h (-1).
Table 17 Tone Generator Control
NOISE GENERATOR
The CS47L24 incorporates a white noise generator, which can be routed within the digital core. The main purpose of the
noise generator is to provide ‘comfort noise’ in cases where silence (digital mute) is not desirable.
Noise Generator (0Dh)
White Noise
Generator
NOISE_GEN_ENA
NOISE_GEN_GAIN
NOISE_GEN_RATE
Figure 23 Digital Core Noise Generator
The noise generator can be selected as input to any of the digital mixers or signal processing functions within the
CS47L24 digital core. The bracketed number (0Dh) in Figure 23 indicates the corresponding *_SRCn register setting for
selection of the noise generator as an input to another digital core function.
The sample rate for the noise generator is configured using the NOISE_GEN_RATE register - see Table 21. Note that
sample rate conversion is required when routing the noise generator output to any signal chain that is asynchronous
and/or configured for a different sample rate.
The noise generator is enabled using the NOISE_GEN_ENA register bit as described in Table 18. The signal level is
configured using NOISE_GEN_GAIN.



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