STM32L4A6XG datasheet(48/282 Pages) STMICROELECTRONICS

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Functional overview

STM32L4A6xG

48/282

DS11584 Rev 8

without having any impact on the timing of “injected” conversions

–

“injected” conversions for precise timing and with high conversion priority

3.25

Random number generator (RNG)

All devices embed an RNG that delivers 32-bit random numbers generated by an integrated

analog circuit.

3.26

Digital camera interface (DCMI)

The devices embed a camera interface that can connect with camera modules and CMOS

sensors through an 8-bit to 14-bit parallel interface, to receive video data. The camera

interface can sustain a data transfer rate up to 54 Mbyte/s at 54 MHz. It features:

•

Programmable polarity for the input pixel clock and synchronization signals

•

Parallel data communication can be 8-, 10-, 12- or 14-bit

•

Supports 8-bit progressive video monochrome or raw bayer format, YCbCr 4:2:2

progressive video, RGB 565 progressive video or compressed data (like JPEG)

•

Supports continuous mode or snapshot (a single frame) mode

•

Capability to automatically crop the image

3.27

Advanced encryption standard hardware accelerator (AES)

The devices embed an AES hardware accelerator can be used to both encipher and

decipher data using AES algorithm.

The AES peripheral supports:

•

Encryption/Decryption using AES Rijndael Block Cipher algorithm

•

NIST FIPS 197 compliant implementation of AES encryption/decryption algorithm

•

128-bit and 256-bit register for storing the encryption, decryption or derivation key (4x

32-bit registers)

•

Electronic codebook (ECB), Cipher block chaining (CBC), Counter mode (CTR), Galois

Counter Mode (GCM), Galois Message Authentication Code mode (GMAC) and Cipher

Message Authentication Code mode (CMAC) supported.

•

Key scheduler

•

Key derivation for decryption

•

128-bit data block processing

•

128-bit, 256-bit key length

•

1x32-bit INPUT buffer and 1x32-bit OUTPUT buffer.

•

One 128-bit Register for the initialization vector when AES is configured in CBC mode

or for the 32-bit counter initialization when CTR mode is selected, GCM mode or

CMAC mode.

•

Automatic data flow control with support of direct memory access (DMA) using 2

channels, one for incoming data, and one for outcoming data.

•

Suspend a message if another message with a higher priority needs to be processed

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