STA450A datasheet(29/66 Pages) STMICROELECTRONICS

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STA450A

HOST_DataPortBitRate

Address

: 0x5F

Type

: R/W

Software Reset

: NA

Hardware Reset

: NA

Description

Data port bit rate / 1K (for bitrates

≥ 128Kbps 0xFF is reported)

10: Synchronised

HOST_EVENTINTE 4-5

Address

: 0x66 - 0x67

Type

: R - W

Software Reset

: NA

Hardware Reset

: NA

Description

These registers are associated to event condition inside the SDEC.

The SDEC contains a 16 bits interrupt register associated with 16 bits enable register.

A bit set in this register will enable the generation of an external interrupt on the interrupt line.

The interrupt associated with each bit is given in the register INT description.

HOST_EVENTINT 4-5

Address

: 0x68 - 0x69

Type

: R - W

Software Reset

: NA

Hardware Reset

: NA

Description

These registers are associated to event condition inside the SDEC.

A bit set in this table indicates the corresponding event has been occurred. Whenever the corresponding

bit in the INTE table has been set an external interrupt is generated.

To clear the bit a fast command has to be issued (see command description).

7654

3210

7654

3210

INTE[15:8]

INTE[7:0]

7654

3210

INT[15:8]

INT[7:0]

Name

Reg

Bit

Comment

Fast extraction Loc0

0x68

0x01

Channel fast extraction for Loc0 successful

Fast extraction Loc1

0x02

Channel fast extraction for Loc1 successful

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