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STA450A bảng dữ liệu(PDF) 24 Page - STMicroelectronics |
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STA450A bảng dữ liệu(HTML) 24 Page - STMicroelectronics |
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24 / 66 page ![]() STA450A 24/66 HOST_STARTUP Address : 0x4D Type : R/W Software Reset : NA Hardware Reset : NA Description Writing 0x01 in this register enables the STA450A sw to leave the wait mode and to start normal process. Using this register is also possible select special mode for silicon evaluation Before to set this register is mandatory to program the system PLL , the Audio Fractional PLL and to configure the PCM output format according to the application DAC. HOST_Pcmdiv Address : 0x4E Type : R/W Software Reset : NA Hardware Reset : NA Description This register is red by STA450A before to leave the wait mode. The SCLK signal is derived from the clock PCMCLK. HOST_pcmdiv = (0_FAC/64) -1 in 16 bit mode HOST_pcmdiv = (0_FAC/128) -1 in 18/20/24 bit mode If Pcm_div is set to 0, the SCLK frequency is equal to the PCMCLK frequency. HOST_Pcmcnf Address : 0x4F Type : R/W Software Reset : NA Hardware Reset : NA Description This register is red by STA450A before to leave the wait mode. Pcm_prec Bit [1:0] 00: 16 bits mode. 01: 18 bits mode 10: 20 bits mode 11: 24 bits mode 7654 3210 4D 7654 3210 4E 7654 3210 4F |
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