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HD64F2145 bảng dữ liệu(PDF) 184 Page - Renesas Technology Corp |
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HD64F2145 bảng dữ liệu(HTML) 184 Page - Renesas Technology Corp |
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184 / 829 page ![]() Rev. 2.0, 08/02, page 144 of 788 7.5 Operation The DTC stores register information in on-chip RAM. When activated, the DTC reads register information in on-chip RAM and transfers data. After the data transfer, the DTC writes updated register information back to on-chip RAM. The pre-storage of register information in memory makes it possible to transfer data over any required number of channels. The transfer mode can be specified as normal, repeat, or block transfer mode. Setting the CHNE bit in MRB to 1 makes it possible to perform a number of transfers with a single activation source (chain transfer). The 24-bit SAR designates the DTC transfer source address, and the 24-bit DAR designates the transfer destination address. After each transfer, SAR and DAR are independently incremented, decremented, or left fixed depending on its register information. Start End Read DTC vector Read register information Data transfer Write register information Clear an activation flag Interrupt exception handling Clear DTCER CHNE = 1 Next transfer Yes Yes No Transfer counter = 0 or DISEL = 1 No Figure 7.4 DTC Operation Flowchart |
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