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HD64F2145 bảng dữ liệu(PDF) 25 Page - Renesas Technology Corp |
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HD64F2145 bảng dữ liệu(HTML) 25 Page - Renesas Technology Corp |
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25 / 829 page  Rev. 2.0, 08/02, page xxiii of xxxviii Figures Section 1 Overview Figure 1.1 Internal Block Diagram of H8S/2140B, H8S/2141B, H8S/2145B, and H8S/2148B ....3 Figure 1.2 Internal Block Diagram of H8S/2160B and H8S/2161B ...............................................4 Figure 1.3 Pin Arrangement of H8S/2140B, H8S/2141B, H8S/2145B, and H8S/2148B ...............5 Figure 1.4 Pin Arrangement of H8S/2160B and H8S/2161B .........................................................6 Section 2 CPU Figure 2.1 Exception Vector Table (Normal Mode) .....................................................................31 Figure 2.2 Stack Structure in Normal Mode .................................................................................31 Figure 2.3 Exception Vector Table (Advanced Mode) .................................................................32 Figure 2.4 Stack Structure in Advanced Mode .............................................................................33 Figure 2.5 Memory Map ........................................................................................................ .......33 Figure 2.6 CPU Internal Registers ................................................................................................34 Figure 2.7 Usage of General Registers..........................................................................................35 Figure 2.8 Stack ............................................................................................................................36 Figure 2.9 General Register Data Formats (1) ..............................................................................38 Figure 2.9 General Register Data Formats (2) ..............................................................................39 Figure 2.10 Memory Data Formats ...............................................................................................40 Figure 2.11 Instruction Formats (Examples).................................................................................52 Figure 2.12 Branch Address Specification in Memory Indirect Addressing Mode ......................55 Figure 2.13 State Transitions ........................................................................................................59 Section 3 MCU Operating Modes Figure 3.1 Address Map for H8S/2140B and H8S/2160B (1) ......................................................71 Figure 3.2 Address Map for H8S/2140B and H8S/2160B (2) ......................................................72 Figure 3.3 Address Map for H8S/2141B and H8S/2161B (1) ......................................................73 Figure 3.4 Address Map for H8S/2141B and H8S/2161B (2) ......................................................74 Figure 3.5 Address Map for H8S/2145BV (1) ..............................................................................75 Figure 3.6 Address Map for H8S/2145BV (2) ..............................................................................76 Figure 3.7 Address Map for H8S/2148B (1).................................................................................77 Section 4 Exception Handling Figure 4.1 Reset Sequence (Mode 3) ............................................................................................81 Figure 4.2 Stack Status after Exception Handling ........................................................................83 Figure 4.3 Operation when SP Value is Odd ................................................................................84 Section 5 Interrupt Controller Figure 5.1 Block Diagram of Interrupt Controller ........................................................................86 Figure 5.2 Relationship between Interrupts IRQ7 and IRQ6, Interrupts KIN15 to KIN0, Interrupts WUE7 to WUE0, and Registers KMIMR, KMIMRA, and WUEMRB ......94 Figure 5.3 Block Diagram of Interrupts IRQ7 to IRQ0 ................................................................95 Figure 5.4 Flowchart of Procedure up to Interrupt Acceptance in Interrupt Control Mode 0 .....100 |
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