HD64F2145 datasheet(72/829 Pages) RENESAS

72 / 829 page

Rev. 2.0, 08/02, page 32 of 788

• Exception vector table and memory indirect branch addresses

In advanced mode, the top area starting at H'00000000 is allocated to the exception vector

table in 32-bit units. In each 32 bits, the upper 8 bits are ignored and a branch address is stored

in the lower 24 bits (see figure 2.3). For details on the exception vector table, see section 4,

Exception Handling.

H'00000000

H'00000003

H'00000004

H'0000000B

H'0000000C

H'00000010

H'00000008

H'00000007

Reserved

Reset exception vector

(Reserved for system use)

Exception vector table

Exception vector 1

(Reserved for system use)

Figure 2.3 Exception Vector Table (Advanced Mode)

The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions

uses an 8-bit absolute address included in the instruction code to specify a memory operand

that contains a branch address. In advanced mode, the operand is a 32-bit longword operand,

providing a 32-bit branch address. The upper 8 bits of these 32 bits are a reserved area that is

regarded as H'00. Branch addresses can be stored in the area from H'00000000 to H'000000FF.

Note that the top area of this range is also used for the exception vector table.

• Stack structure

In advanced mode, when the program counter (PC) is pushed onto the stack in a subroutine

call, and the PC and condition-code register (CCR) are pushed onto the stack in exception

handling, they are stored as shown in figure 2.4. The extended control register (EXR) is not

pushed onto the stack. For details, see section 4, Exception Handling.

HD64F2145 bảng dữ liệu(PDF) 72 Page - Renesas Technology Corp