HD64F2145 datasheet(81/829 Pages) RENESAS

81 / 829 page

Rev. 2.0, 08/02, page 41 of 788

2.6

Instruction Set

The H8S/2000 CPU has 65 types of instructions. The instructions are classified by function as

shown in table 2.1.

Table 2.1

Instruction Classification

Function

Instructions

Size

Types

MOV

B/W/L

POP*

1, PUSH*1

W/L

LDM*

5, STM*5

Data transfer

MOVFPE*

3, MOVTPE*3

ADD, SUB, CMP, NEG

B/W/L

ADDX, SUBX, DAA, DAS

INC, DEC

B/W/L

ADDS, SUBS

MULXU, DIVXU, MULXS, DIVXS

B/W

EXTU, EXTS

W/L

Arithmetic

operations

TAS*

Logic operations

AND, OR, XOR, NOT

B/W/L

Shift

SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL,

ROTXR

B/W/L

Bit manipulation

BSET, BCLR, BNOT, BTST, BLD, BILD, BST, BIST, BAND,

BIAND, BOR, BIOR, BXOR, BIXOR

B14

Branch

CC*

2, JMP, BSR, JSR, RTS

—

System control

TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC,

NOP

—9

Block data transfer EEPMOV

—

Total: 65

Notes: B: Byte size; W: Word size; L: Longword size.

1. POP.W Rn and PUSH.W Rn are identical to MOV.W @SP+, Rn and MOV.W Rn, @-

SP. POP.L ERn and PUSH.L ERn are identical to MOV.L @SP+, ERn and MOV.L ERn,

@-SP.

2. B

CC is the general name for conditional branch instructions.

3. Cannot be used in this LSI.

4. When using the TAS instruction, use registers ER0, ER1, ER4, and ER5.

5. ER7 is not used as the register that can be saved (STM)/restored (LDM) when using

STM/LDM instruction, because ER7 is the stack pointer.

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