HD64F2145 datasheet(181/829 Pages) RENESAS

181 / 829 page

Rev. 2.0, 08/02, page 141 of 788

diagram of DTC activation source control. For details on the interrupt controller, see section 5,

Interrupt Controller.

CPU

DTC

DTCER

Source flag cleared

On-chip

peripheral

module

IRQ interrupt

Interrupt

request

Clear

controller

Clear request

Interrupt controller

Interrupt mask

Select

DTVECR

Figure 7.2 Block Diagram of DTC Activation Source Control

7.4

Location of Register Information and DTC Vector Table

Locate the register information in the on-chip RAM (addresses: H'(FF)EC00 to H'(FF)EFFF).

The method for locating the register information in address space is shown in figure 7.3. Locate

MRA, SAR, MRB, DAR, CRA, and CRB, in that order, from the start address of the register

information. In the case of chain transfer, register information should be located in consecutive

areas as shown in figure 7.3, and the register information start address should be located at the

vector address corresponding to the interrupt source in the DTC vector table. The DTC reads the

start address of the register information from the vector table set for each activation source, and

then reads the register information from that start address.

When the DTC is activated by software, the vector address is obtained from: H'0400 +

(DTVECR[6:0]

× 2). For example, if DTVECR is H'10, the vector address is H'0420.

The configuration of the vector address is the same in both normal and advanced modes; a 2-byte

unit is used in both cases. Specify the lower two bits of the register information start address.

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