HD64F2145 datasheet(178/829 Pages) RENESAS

178 / 829 page

Rev. 2.0, 08/02, page 138 of 788

7.2.2

DTC Mode Register B (MRB)

MRB selects the DTC operating mode.

Bit

Bit Name

Initial Value

R/W

Description

CHNE

Undefined

—

DTC Chain Transfer Enable

When this bit is set to 1, a chain transfer will be

performed. For details, refer to section 7.5.4, Chain

Transfer.

In data transfer with CHNE set to 1, determination of the

end of the specified number of data transfers, clearing

of the interrupt source flag, and clearing of DTCER are

not performed.

DISEL

Undefined

—

DTC Interrupt Select

When this bit is set to 1, a CPU interrupt request is

generated every time data transfer ends (the DTC

clears the interrupt source flag for the activation

source). When this bit is cleared to 0, a CPU interrupt

request is generated only when the specified number of

data transfer ends (the DTC does not clear the interrupt

source flag for the activation source).

—

Undefined

—

Reserved

These bits have no effect on DTC operation. Only 0

should be written to these bits.

7.2.3

DTC Source Address Register (SAR)

SAR is a 24-bit register that designates the source address of data to be transferred by the DTC.

For word-size transfer, specify an even source address.

7.2.4

DTC Destination Address Register (DAR)

DAR is a 24-bit register that designates the destination address of data to be transferred by the

DTC. For word-size transfer, specify an even destination address.

7.2.5

DTC Transfer Count Register A (CRA)

CRA is a 16-bit register that designates the number of times data is to be transferred by the DTC.

In normal mode, the entire CRA functions as a 16-bit transfer counter (1 to 65536). It is

decremented by 1 every time data is transferred, and transfer ends when the count reaches H'0000.

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