HD64F2145 datasheet(186/829 Pages) RENESAS

tên linh kiện	HD64F2145

Giải thích chi tiết về linh kiện	Hitachi 16-Bit Single-Chip Microcomputer

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Rev. 2.0, 08/02, page 146 of 788

Table 7.3

Name

Abbreviation

Function

DTC source address register

SAR

Transfer source address

DTC destination address register

DAR

Transfer destination address

DTC transfer count register AH

CRAH

Holds number of transfers

DTC transfer count register AL

CRAL

Transfer Count

DTC transfer count register B

CRB

Not used

Transfer

SAR

DAR

SAR

Repeat area

Figure 7.6 Memory Mapping in Repeat Mode

7.5.3

Block Transfer Mode

In block transfer mode, one activation source transfers one block of data. Either the transfer source

or the transfer destination is designated as a block area. Table 7.4 lists the register functions in

block transfer mode. The block size can be between 1 and 256. When the transfer of one block

ends, the initial state of the block size counter and the address register that is specified as the block

area is restored. The other address register is then incremented, decremented, or left fixed

according to the register information. From 1 to 65,536 transfers can be specified. Once the

specified number of transfers have been completed, a CPU interrupt is requested.

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