HD64F2145 datasheet(145/829 Pages) RENESAS

145 / 829 page

Rev. 2.0, 08/02, page 105 of 788

5.6.4

Interrupt Response Times

Table 5.5 shows interrupt response times

− the intervals between generation of an interrupt request

and execution of the first instruction in the interrupt handling routine. The execution status

symbols used in table 5.5 are explained in table 5.6.

Table 5.5

Interrupt Response Times

No.

Execution Status

Normal Mode

Advanced Mode

Interrupt priority determination*

Number of wait states until executing

instruction ends*

1 to (19 + 2·SI)

PC, CCR stack save

2·SK

Vector fetch

2·SI

Instruction fetch*

2·SI

Internal processing*

Total (using on-chip memory)

11 to 31

12 to 32

Notes: 1. Two states in case of internal interrupt.

2. Refers to MULXS and DIVXS instructions.

3. Prefetch after interrupt acceptance and prefetch of interrupt handling routine.

4. Internal processing after interrupt acceptance and internal processing after vector fetch.

Table 5.6

Number of States in Interrupt Handling Routine Execution Status

Object of Access

External Device

8-Bit Bus

16-Bit Bus

Symbol

Internal

Memory

2-State

Access

3-State

Access

2-State

Access

3-State

Access

Instruction fetch SI

Branch address read SJ

Stack manipulation SK

6 + 2m

3 + m

Legend

Number of wait states in external device access

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