HD64F2145 datasheet(149/829 Pages) RENESAS

tên linh kiện	HD64F2145

Giải thích chi tiết về linh kiện	Hitachi 16-Bit Single-Chip Microcomputer

PDF	829 Pages

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nhà sản xuất	RENESAS [Renesas Technology Corp]

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149 / 829 page

Rev. 2.0, 08/02, page 109 of 788

5.7.4

Usage Notes

1. In an address break, the break address should be an address where the first byte of the

instruction exists. Otherwise, a break condition will not be satisfied.

2. In normal mode, addresses A23 to A16 are not compared.

3. When the branch instructions (Bcc, BSR), jump instructions (JMP, JSR), RST instruction, and

RTE instruction are placed immediately prior to the address specified by BAR, a prefetch

signal to the address may be output to request an address break by executing these instruction.

It is necessary to take countermeasures: do not set a break address to an address immediately

after these instructions, or determine whether interrupt handling is performed by satisfaction of

a normal condition.

4. An address break interrupt is generated by combining the internal prefetch signal and an

address. Therefore, the timing to enter the interrupt exception handling differs according to the

instructions at the specified and at prior addresses and execution cycles.

Figure 5.10 shows an example of address timing.

HD64F2145 bảng dữ liệu(PDF) 149 Page - Renesas Technology Corp