HD64F2145 datasheet(141/829 Pages) RENESAS

141 / 829 page

Rev. 2.0, 08/02, page 101 of 788

5.6.2

Interrupt Control Mode 1

In interrupt control mode 1, mask control is applied to three levels for IRQ and on-chip peripheral

module interrupt requests by comparing the I and UI bits in CCR in the CPU, and the ICR setting.

• An interrupt request with interrupt control level 0 is accepted when the I bit in CCR is cleared

to 0. When the I bit is set to 1, the interrupt request is held pending

• An interrupt request with interrupt control level 1 is accepted when the I bit or UI bit in CCR is

cleared to 0. When both I and UI bits are set to 1, the interrupt request is held pending.

For instance, the state transition when the interrupt enable bit corresponding to each interrupt is set

to 1, and ICRA to ICRC are set to H’20, H’00, and H’00, respectively (IRQ2 and IRQ3 interrupts

are set to control level 1, and other interrupts are set to control level 0) is shown below. Figure 5.5

shows a state transition diagram.

• All interrupt requests are accepted when I = 0. (Priority order: NMI > IRQ2 > IRQ3 > address

break > IRQ0 > IRQ1 …)

• Only NMI, IRQ2, IRQ3 and address break interrupt requests are accepted when I = 1 and UI =

• Only an NMI and address break interrupt request is accepted when I = 1 and UI = 1.

Only NMI and address break

interrupt requests are accepted

All interrupt requests

are accepted

Exception handling execution

or I

1, UI

Exception handling

execution or UI

Only NMI, address break, IRQ2,

and IRQ3 interrupt requests

are accepted

Figure 5.5 State Transition in Interrupt Control Mode 1

Figure 5.6 shows a flowchart of the interrupt acceptance operation.

1. If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an

interrupt request is sent to the interrupt controller.

2. According to the interrupt control level specified in ICR, the interrupt controller only accepts

an interrupt request with interrupt control level 1 (priority), and holds pending an interrupt

request with interrupt control level 0 (no priority). If several interrupt requests are issued, an

interrupt request with the highest priority is accepted according to the priority order, an

interrupt handling is requested to the CPU, and other interrupt requests are held pending.

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