GS3471 datasheet(93/179 Pages) SEMTECH

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GS3471

Final Data Sheet Rev.4

PDS-060498

September 2017

93 of 179

Semtech

www.semtech.com

Figure 4-53: GSPI_BUS_THROUGH_ENABLE Operation

4.22.4 SCLK Pin

The SCLK pin is the GSPI serial data shift clock input to the device, and must be provided

by the host processor.

Serial data is clocked into the GS3471 SDIN pin on the rising edge of SCLK. Serial data is

clocked out of the device from the SDOUT pin on the falling edge of SCLK (read

operation). SCLK is ignored when CS is HIGH.

4.22.5 Command Word Description

All GSPI accesses are a minimum of 32 bits in length (a 16-bit Command Word followed

by a 16-bit Data Word) and the start of each access is indicated by the high-to-low

transition of the chip select (CS) pin of the GS3471.

The format of the Command Word and Data Words are shown in Figure 4-54.

Data received immediately following this high-to-low transition will be interpreted as a

new Command Word.

4.22.5.1 R/W bit - B15 Command Word

This bit indicates a read or write operation.

When R/W is set to 1, a read operation is indicated, and data is read from the register

specified by the ADDRESS field of the Command Word.

When R/W is set to 0, a write operation is indicated, and data is written to the register

specified by the ADDRESS field of the Command Word.

SDIN pin

SDOUT pin

GSPI_LINK

_DISABLE

BUS_THROUGH

CS pin

High-Z

Configuration and

Status Register

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