GS3471 datasheet(62/179 Pages) SEMTECH

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GS3471

Final Data Sheet Rev.4

PDS-060498

September 2017

62 of 179

Semtech

www.semtech.com

4.18.2 Line Based CRC Error Detection

The GS3471 calculates line based CRCs for HD and 3G video signals. CRC calculations are

performed for each 10-bit channel (Y and C for HD video, DS1 and DS2 for 3G video).

If a mismatch in the calculated and received CRC values is detected for Y channel data

(Data Stream 1 for 3G video), the YCRC_ERR bit in the ERROR_STAT_[2:1] register is set

HIGH.

If a mismatch in the calculated and received CRC values is detected for C channel data

(Data Stream 2 for 3G video), the CCRC_ERR bit in the ERROR_STAT_[2:1] register is set

HIGH.

Y or C CRC errors are also generated if CRC values are not embedded.

3G Level B signals all consist of two data streams. Each data stream is a multiplex of a C

channel and a Y channel. Each channel of each data stream has CRC.

For 3G Level B formats, YCRC errors are detected for both of the two Y channels, and

CCRC errors are detected for both of the two C channels.

Note: By default, 8-bit to 10-bit TRS remapping is enabled. If an 8-bit input is used, the

HD CRC check is based on the 10-bit remapped value, not the 8-bit value, so the CRC

Error Flag is incorrectly asserted and should be ignored. If 8-bit to 10-bit remapping is

enabled, then CRC insertion should be enabled by setting the CRC_INS_DS[2:1]_MASK

bit LOW in the IOPROC_1 or IOPROC_2 register. This ensures that the CRC values are

updated.

4.18.3 EDH CRC Error Detection

The GS3471 also calculates Full Field (FF) and Active Picture (AP) CRC's according to

SMPTE RP165 in support of Error Detection and Handling packets in SD signals.

These calculated CRC values are compared with the received CRC values.

Error flags for AP and FF CRC errors are provided and each error flag is a logical OR of

field 1 and field 2 error conditions.

The AP_CRC_ERR bit in the ERROR_STAT_[2:1] register is set HIGH when an Active

Picture CRC mismatch has been detected in field 1 or 2.

The FF_CRC_ERR bit in the ERROR_STAT_[2:1] register is set HIGH when a Full Field

CRC mismatch has been detected in field 1 or 2.

EDH CRC errors are only indicated when the device is operating in SD mode and when

the device has correctly received EDH packets.

4.18.4 HD & 3G Line Number Error Detection

If a mismatch in the calculated and received line numbers is detected, the LNUM_ERR

bit in the ERROR_STAT_[2:1] register is set HIGH.

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