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GS3471 bảng dữ liệu(PDF) 67 Page - Semtech Corporation

tên linh kiện GS3471
Giải thích chi tiết về linh kiện  3G, HD, SD SDI Receiver, with Integrated Adaptive Cable Equalizer
PDF  179 Pages
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nhà sản xuất  SEMTECH [Semtech Corporation]
Trang chủ  http://www.semtech.com
Logo SEMTECH - Semtech Corporation

GS3471 bảng dữ liệu(HTML) 67 Page - Semtech Corporation

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GS3471
Final Data Sheet Rev.4
PDS-060498
September 2017
67 of 179
Semtech
www.semtech.com
4.19.3 Ancillary Data Checksum Error
The GS3471 calculates checksums for all received ancillary data. These calculated
checksums are compared with the received ancillary data checksum words.
If a mismatch in the calculated and received checksums is detected, then a checksum
error is indicated.
When operating in HD mode, the device makes comparisons on both the Y and C
channels separately. If an error condition in the Y channel is detected, the
YCS_ERR_[2:1] bit in the ERROR_STAT_[2:1] register is set HIGH. If an error condition
in the C channel is detected, the CCS_ERR_[2:1] bit in the ERROR_STAT_[2:1] register
is set HIGH.
When operating in 3G Level A mode, the device makes comparisons on both the Y (Data
Stream 1) and C (Data Stream 2) channels separately. If an error condition in the Y
channel is detected, the YCS_ERR_[2:1] bit in the ERROR_STAT_[2:1] register is set
HIGH. If an error condition in the C channel is detected, the CCS_ERR_[2:1] bit in the
ERROR_STAT_[2:1] register is set HIGH.
When operating in 3G Level B mode, the device makes comparisons on both the Y
channel and the C channel of both Link A and Link B. For Link A, if an error condition in
the Y channel is detected, the YCS_ERR_[2:1] bit in the ERROR_STAT_1 register is set
HIGH. If an error condition in the C channel is detected, the CCS_ERR_[2:1] bit in the
ERROR_STAT_1 register is set LOW. For Link B, if an error condition in the Y channel is
detected, the YCS_ERR_[2:1] bit in the ERROR_STAT_2 register is set HIGH. If an error
condition in the C channel is detected, the CCS_ERR_[2:1] bit in the ERROR_STAT_2
register is set LOW.
When operating in SD mode, only the YCS_ERR_[2:1] bit is set HIGH when checksum
errors are detected.
4.20 Signal Processing
4.20.1 Audio De-Embedding Mode
The GS3471 includes an integrated audio de-embedder which is active when the
deserializer is configured for SMPTE mode unless disabled using the AUDIO_EN/DIS pin.
In non-SMPTE modes, the audio de-embedder is powered down to reduce power
consumption. All output pins are LOW when the de-embedder is powered down.
For detailed description of this feature, refer to Section 4.21.



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