ML9092-01TB datasheet(15/66 Pages) OKI

15 / 66 page

FEDL9092-01

OKI Semiconductor

ML9092-01/02/03/04

15/66

•

Chip select input pin. A Schmitt circuit is internally connected to this pin. An “L” level selects the chip, and an

“H” level does not select the chip. During the “L” level, internal registers can be accessed.

•

Clock input pin for serial interface data I/O. A Schmitt circuit is internally connected to this pin. Data input to the

DI/O pin is synchronized to the rising edge of the clock. Output from the DI/O pin is synchronized to the falling

edge of the clock.

• DI/O

Serial interface data I/O pin. A Schmitt circuit is internally connected to this pin. This pin is in the output state

only during the interval beginning when commands for key scan data read, RAM read or rotary encoder are written

until the

CS signal rises. At all other times this pin is in the input state. (When reset, the input state is set.) The

relation between data level of this pin and operation is listed below.

Data level

LCD display

Key status

Rotary switch

“H”

Light ON

Count value

“L”

Light OFF

OFF

Count value

• KREQ

Key scan read and rotary encoder read READY signal output pin.

• OSC1

Input pin for RC oscillation. A Schmitt circuit is internally connected to this pin. An oscillation circuit is

configured by connecting this pin and OSC2 with a resistor (R) placed across the connection (see figure below).

Make the wiring between this pin and the resistor as short as possible. If an external master oscillation clock is to

be input, input the master oscillation clock to this pin.

OSC1

OSC2

R = 56 k

Ω

(VDD = 4.5 to 5.5 V)

• OSC2

Output pin for RC oscillation. A Schmitt circuit is internally connected to this pin. An oscillation circuit is

configured by connecting this pin and OSC1 with a resistor (R) placed across the connection (see figure above).

Make the wiring between this pin and the resistor as short as possible. If an external master oscillation clock is to

be input, leave this pin unconnected (open).

•

RESET

Reset signal input pin. A Schmitt circuit is internally connected to this pin. The initial state can be set by pulling

this pin to an “L” level. Refer to the “Output, I/O and Register States in Response to Reset Input” page for the

initial states of each register and display.

An internal pull-up resistor is connected to this pin. Connecting an external capacitor enables power-on reset.

• TEST

Test signal input pin. Connect this pin to VSS.

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