ML9092-01TB datasheet(46/66 Pages) OKI

46 / 66 page

FEDL9092-01

OKI Semiconductor

ML9092-01/02/03/04

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• Port register C (PTC) set

—

PTC4

PTC3

PTC2

PTC1

PTC0

—: don’t care

The port register C set instruction sets the output of port C. (Applies to the ML9092-01 only.)

This register is enabled when a “L” level is applied to the KPS pin of ML9092-01 and the R0/C0 to R4/C4 pins are

set as port C.

When each bit of PTC4 to PTC0 is set to “1”, a “H” level is output from each of the R4/C4 to R0/C0 pins of the

general purpose port C. In the same way, when each bit of PTC4 to PTC0 is set to “0”, a “H” level is output from

each of the R4/C4 to R0/C0 pins. If the

RESET pin is pulled to a “L” level, the PE bit (bit D2) of the control

After the reset state is released, if the PTC4 to PTC0 bits of this register are set to “1” or “0” and then the PE bit is

set to “1”, the R4/C4 to R0/C0 pins are released from its high impedance state and a “H” or “L” level that

corresponds to the set status of each bit of PTC4 to PTC0, is output from the R4/C4 to R0/C0 pins.

• Port register D (PTD) set

—

PTD4

PTD3

PTD2

PTD1

PTD0

—: don’t care

The port register D set instruction sets the output of port D. (Applies to the ML9092-01 only.)

This register is enabled when a “L” level is applied to the KPS pin of ML9092-01 and the C0/D0 to C4/D4 pins are

set as port C.

When each bit of PTD4 to PTD0 is set to “1”, a “H” level is output from each of the C4/D4 to C0/D0 pins of the

general purpose port D. In the same way, when each bit of PTD4 to PTD0 is set to “0”, a “H” level is output from

each of the C4/D4 to C0/D0 pins. If the

RESET pin is pulled to a “L” level, the PE bit (bit D2) of the control

After the reset state is released, if the PTD4 to PTD0 bits of this register are set to “1” or “0” and then the PE bit is

set to “1”, the C4/D4 to C0/D0 pins are released from its high impedance state and a “H” or “L” level that

corresponds to the set status of each bit of PTD4 to PTD0, is output from the C4/D4 to C0/D0 pins.

• Control register 1 (FCR1)

INC

WLS

SHL

DTY1

DTY0

(1) D7 (INC) Address increment direction

1: X direction address increment

0: Y direction address increment

This bit sets the address increment direction of the display RAM. The display RAM address is automatically

incremented by 1 every time data is written to the display data register. Writing a “1” to this bit sets “X address

increment,” and writing a “0” sets “Y address increment.” For further details regarding address incrementing,

refer to the page entitled “X, Y Address Counter Auto Increment.” This bit is set to “1” if the

RESET pin is pulled

to a “L” level.

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