MMPF0200 datasheet(61/114 Pages) NXP

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NXP Semiconductors

PF0200

FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS

6.4.6

LDO regulators description

This section describes the LDO regulators provided by the PF0200. All regulators use the main bandgap as reference. Refer to Bias and

references block description section for further information on the internal reference voltages.

A Low Power mode is automatically activated by reducing bias currents when the load current is less than I_Lmax/5. However, the lowest

bias currents may be attained by forcing the part into its Low Power mode by setting the VGENxLPWR bit. The use of this bit is only

recommended when the load is expected to be less than I_Lmax/50, otherwise performance may be degraded.

When a regulator is disabled, the output will be discharged by an internal pull-down. The pull-down is also activated when RESETBMCU

is low.

Figure 19. General LDO block diagram

Switch mode supply SWBST (continued)

tSWBSTTR

Transient Load Response

ISWBST from 1.0 to 100 mA in 1.0 µs

Time to settle 80% of transient

–

500

µs

tSWBSTTR

Transient Load Response

ISWBST from 100 to 1.0 mA in 1.0 µs

Time to settle 80% of transient

––

ISWBSTHSQ

NMOS Off Leakage

SWBSTIN = 4.5 V, SWBSTMODE [1:0] = 00

–1.0

5.0

µA

tONSWBST

Turn-on Time

Enable to 90% of VSWBST, ISWBST = 0.0 mA

––

2.0

fSWBST

Switching Frequency

–

2.0

–

MHz

ηSWBST

Efficiency

ISWBST = ISWBSTMAX

–86–

Notes

54.

Only in Auto mode.

Table 74. SWBST electrical specifications (continued)

All parameters are specified at Consumer TA = -40 to 85 °C and Extended Industrial TA = -40 to 105 °C, VIN = VINSWBST = 3.6 V,

VSWBST = 5.0 V, ISWBST = 100 mA, typical external component values, fSWBST = 2.0 MHz, otherwise noted. Typical values are

characterized at VIN = VINSWBST = 3.6 V, VSWBST = 5.0 V, ISWBST = 100 mA, and 25 °C, unless otherwise noted.

Symbol

Parameters

Min.

Typ.

Max.

Units

Notes

VGENx

VINx

VGENx

CGENx

VGENxEN

VGENxLPWR

VREF

VGENx

Interface

Discharge

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