ADAU1977WBCPZ-R7 datasheet(18/68 Pages) AD

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ADAU1977

Data Sheet

Rev. C | Page 18 of 68

MICROPHONE BIAS

The microphone bias is generated by the input voltage at the

VBOOST_IN pin (Pin 26) via a linear regulator to ensure low

noise performance and to reject the high frequency noise from

the boost converter. If the internal boost converter output is

used, the VBOOST_OUT pin (Pin 25) must be connected to

the VBOOST_IN pin (Pin 26). If an external supply is used for

the microphone bias, the supply can be fed at the VBOOST_IN

pin (Pin 26); in this case, leave the VBOOST_OUT pin (Pin 25)

open. The microphone bias voltage is programmable from 5 V

to 9 V by using the MB_VOLTS bits (Bits[7:4] of Register 0x03).

The microphone bias output voltage is available at the MICBIAS pin

(Pin 27). This pin can be decoupled to AGND using a maximum of

up to a 10 µF capacitor with an ESR of at least 1 Ω. For higher

value capacitors, especially those above 1 nF, the ESR of the capa-

citor should be ≥ 1 Ω to ensure the stability of the microphone

bias regulator. Register 0x03 can be used to enable the microphone

bias. Table 11 lists the switching frequency of the boost converter

based on the inductor value and common sample rates.

ANALOG INPUTS

The ADAU1977 has four differential analog inputs. The ADCs

can accommodate both dc- and ac-coupled input signals.

The block diagram shown in Figure 16 represents the typical

input circuit.

In most audio applications, the dc content of the signal is removed

by using a coupling capacitor. However, the ADAU1977 consists

of a unique input structure that allows direct coupling of the

input signal, eliminating the need for using a large coupling

capacitor at the input. Each input has a fixed 14 dB attenuator

connected to AGND for accommodating a 10 V rms differential

input. The typical input resistance is approximately 26 kΩ from

each input to AGND.

In dc-coupled applications, if the VCM at AINxP and AINxN is

the same, the dc content in the ADC output is close to 0. If the

input pins are presented with different common-mode dc levels,

the difference between the two levels appears at the ADC output

and can be removed by enabling the high-pass filter.

The high-pass filter has a 1.4 Hz, 6 dB per octave cutoff at a

48 kHz sample rate. The cutoff frequency scales directly with

the sample frequency. However, care is required in dc-coupled

applications to ensure that the common-mode dc voltage does

not exceed the specified limit. The common-mode loop can

accommodate a common-mode dc voltage from 0 V to 7 V. The

input required for the full-scale ADC output (0 dBFS) is typically

10 V rms differential.

Figure 16. Analog Input Block

VREF

AINxP

AINxN

VID = V INPUT DIFFERENTIAL

VICM+ = VCM AT AINx+

VICM– = VCM AT AINx–

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