ADAU1977WBCPZ-R7 datasheet(31/68 Pages) AD

31 / 68 page

Data Sheet

ADAU1977

Rev. C | Page 31 of 68

I2C MODE

The ADAU1977 supports a 2-wire serial (I2C-compatible) bus

protocol. Two pins—serial data (SDA) and serial clock (SCL)—

are used to communicate with the system I2C master controller.

In I2C mode, the ADAU1977 is always a slave on the bus, meaning

that it cannot initiate a data transfer. Each slave device on the

I2C bus is recognized by a unique device address. The device

address and R/W byte for the ADAU1977 are shown in Table 21.

The address resides in the first seven bits of the I2C write. Bit 7

and Bit 6 of the I2C address for the ADAU1977 are set by the

levels on the ADDR1 and ADDR0 pins. The LSB of the first I2C

byte (the R/W bit) from the master identifies whether it is a read

or write operation. Logic Level 1 in LSB corresponds to a read

operation, and Logic Level 0 corresponds to a write operation.

Table 21. ADAU1977 I2C First Byte Format

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

ADDR1

ADDR0

R/W

The first seven bits of the I2C chip address for the ADAU1977

are xx10001. Bit 0 and Bit 1 of the address byte can be set using

the ADDR1 and ADDR0 pins to set the chip address to the

desired value.

The 7-bit I2C device address can be set to one of four possible

options using the ADDR1 and ADDR0 pins:

•

I2C Device Address 0010001 (0x11)

•

I2C Device Address 0110001 (0x31)

•

I2C Device Address 1010001 (0x51)

•

I2C Device Address 1110001 (0x71)

In I2C mode, both the SDA and SCL pins require that an

appropriate pull-up resistor be connected to IOVDD. The

voltage on these signal lines should not exceed the voltage on

the IOVDD pin. Figure 46 shows a typical connection diagram

for the I2C mode.

The value of the pull-up resistor for the SDA or SCL pin can be

calculated as follows.

Minimum RPULL UP = (IOVDD – VIL)/ISINK

where:

IOVDD is the I/O supply voltage, typically ranging from 1.8 V

up to 3.3 V.

VIL is the maximum voltage at Logic Level 0 (that is, 0.4 V, as

per the I2C specifications).

ISINK is the current sink capability of the I/O pin.

The SDA pin can sink 2 mA current; therefore, the minimum

value of RPULL UP for an IOVDD of 3.3 V is 1.5 kΩ.

Depending on the capacitance of the board, the speed of the bus

can be restricted to meet the rise time and fall time specifications.

For fast mode with a bit rate time of around 1 Mbps, the rise

time must be less than 550 ns. Use the following equation to

determine whether the rise time specification can be met:

t = 0.8473 × RPULL UP × CBOARD.

To meet the 300 ns rise time requirement, the CBOARD must be

less than 236 pF.

For the SCL pin, the calculations depend on the current sink

capability of the I2C master used in the system.

Addressing

Initially, each device on the I2C bus is in an idle state and monitors

the SDA and SCL lines for a start condition and the proper address.

The I2C master initiates a data transfer by establishing a start

condition, defined by a high-to-low transition on SDA while

SCL remains high. This indicates that an address/data stream

follows. All devices on the bus respond to the start condition

and acquire the next eight bits from the master (the 7-bit address

plus the R/W bit) MSB first. The master sends the 7-bit device

address with the read/write bit to all the slaves on the bus. The

device with the matching address responds by pulling the data

line (SDA) low during the ninth clock pulse. This ninth bit is

known as an acknowledge bit. All other devices withdraw from

the bus at this point and return to the idle condition.

The R/W bit determines the direction of the data. A Logic 0 on the

LSB of the first byte means that the master is to write information

to the slave, whereas a Logic 1 means that the master is to read

information from the slave after writing the address and repeating

the start address. A data transfer takes place until a master initiates

a stop condition. A stop condition occurs when SDA transitions

from low to high while SCL is held high.

Stop and start conditions can be detected at any stage during

the data transfer. If these conditions are asserted out of sequence

during normal read and write operations, the ADAU1977

immediately jumps to the idle condition.

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