ADAU1977WBCPZ-R7 datasheet(15/68 Pages) AD

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Data Sheet

ADAU1977

Rev. C | Page 15 of 68

THEORY OF OPERATION

OVERVIEW

The ADAU1977 incorporates four high performance ADCs

with an integrated boost converter for microphone bias, the

associated microphone diagnostics for fault detection, and a

phase-locked loop circuit for generating the necessary on-chip

clock signals.

POWER SUPPLY AND VOLTAGE REFERENCE

The ADAU1977 requires a single 3.3 V power supply. Separate

power supply input pins are provided for the analog and boost

converter. These pins should be decoupled to AGND with 100 nF

ceramic chip capacitors placed as close as possible to the pins to

minimize noise pickup. A bulk aluminum electrolytic capacitor

of at least 10 μF must be provided on the same PCB as the ADC.

It is important that the analog supply be as clean as possible for

best performance.

The supply voltage for the digital core (DVDD) is generated

using an internal low dropout regulator. The typical DVDD

output is 1.8 V and must be decoupled using a 100 nF ceramic

capacitor and a 10 µF capacitor. Place the 100 nF ceramic

capacitor as close as possible to the DVDD pin.

The voltage reference for the analog blocks is generated

internally and output at the VREF pin (Pin 2). The typical

voltage at the pin is 1.5 V with an AVDDx of 3.3 V.

All digital inputs are compatible with TTL and CMOS levels.

All outputs are driven from the IOVDD supply. The IOVDD

can be in the range of 1.8 V to 3.3 V. The IOVDD pin must

be decoupled with a 100 nF capacitor placed as close to the

IOVDD pin as possible. It is recommended to connect the

AGND, DGND, PGND, and exposed pad to a single GND

plane on the PCB for best performance.

The ADC internal voltage reference is output from the VREF pin

and should be decoupled using a 100 nF ceramic capacitor in

parallel with a 10 μF capacitor. The VREF pin has limited

current capability. The voltage reference is used as a reference to

the ADC; therefore, it is recommended not to draw current

from this pin for external circuits. When using this reference,

use a noninverting amplifier buffer to provide a reference to

other circuits in the application.

In reset mode, the VREF pin is disabled to save power and is

enabled only when the RST pin is pulled high.

POWER-ON RESET SEQUENCE

The ADAU1977 requires that a single 3.3 V power supply be

provided externally at the AVDDx pin. The part internally generates

DVDD (1.8 V), which is used for the digital core of the ADC.

The DVDD supply output pin (Pin 10) is provided to connect

the decoupling capacitors to DGND. The typical recommended

values for the decoupling capacitors are 100 nF in parallel with

10 µF. During a reset, the DVDD regulator is disabled to reduce

power consumption. After the PD/RST pin (Pin 6) is pulled high,

the part enables the DVDD regulator. However, the internal ADC

and digital core reset is controlled by the internal POR signal

(power-on reset) circuit, which monitors the DVDD level.

Therefore, the device does not come out of a reset until DVDD

reaches 1.2 V and the POR signal is released. The DVDD settling

time depends on the charge-up time for the external capacitors

and on the AVDDx ramp-up time.

The internal POR circuit is provided with hysteresis to ensure

that a reset of the part is not initiated by an instantaneous glitch

on DVDD. The typical trip points are 1.2 V with RST high and

0.6 V (±20%) with RST low. This ensures that the core is not

reset until the DVDD level falls below the 0.6 V trip point.

As soon as the PD/RST pin is pulled high, the internal regulator

starts charging up the CEXT on the DVDD pin. The DVDD charge-

up time is based on the output resistance of the regulator and

the external decoupling capacitor. The time constant can be

calculated as

tC = ROUT × CEXT (ROUT = 20 Ω typical)

For example, if CEXT is 10 µF, then tC is 200 µs and is the time to

reach the DVDD voltage, within 63.6%.

The POR circuit releases an internal reset of the core when DVDD

reaches 1.2 V (see Figure 13). Therefore, it is recommended to

wait for at least the tC period to elapse before sending I2C or SPI

control signals.

Figure 13. Power-On Reset Timing

When applying a hardware reset to the part by pulling the

PD/RST pin (Pin 6) low and then high, there are certain time

restrictions. During the RST low pulse period, the DVDD starts

discharging. The discharge time constant is decided by the internal

resistance of the regulator and CEXT. The time required for DVDD

to fall from 1.8 V to 0.48 V (0.6 V − 20%) can be estimated using

the following equation:

tD = 1.32 × RINT × CEXT

where RINT = 64 kΩ typical. (RINT can vary due to process by ±20%.)

For example, if CEXT is 10 µF, then tD is 0.845 sec.

1.2V

0.48V

POR

DVDD (1.8V)

PD/RST

AVDDx

tRESET

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