PC7447 datasheet(5/66 Pages) ATMEL

5 / 66 page

PC7457/47 [Preliminary]

5345B–HIREL–02/04

–

Four integer units (IUs) that share 32 GPRs for integer operands

Three identical IUs (IU1a, IU1b, and IU1c) can execute all integer

instructions except multiply, divide, and move to/from special-purpose

IU2 executes miscellaneous instructions including the CR logical operations,

integer multiplication and division instructions, and move to/from special-

purpose register instructions

–

Five-stage FPU and a 32-entry FPR file

Fully IEEE 754-1985-compliant FPU for both single- and double-precision

operations

Supports non-IEEE mode for time-critical operations

Hardware support for denormalized numbers

Thirty-two 64-bit FPRs for single- or double-precision operands

–

Four vector units and 32-entry vector register file (VRs)

Vector permute unit (VPU)

Vector integer unit 1 (VIU1) handles short-latency AltiVec

™

integer

instructions, such as vector add instructions (vaddsbs, vaddshs, and

vaddsws, for example)

Vector integer unit 2 (VIU2) handles longer-latency AltiVec integer

instructions,

such

vector

multiply

add

instructions

(vmhaddshs,

vmhraddshs, and vmladduhm, for example)

Vector floating-point unit (VFPU)

–

Three-stage load/store unit (LSU)

Supports integer, floating-point, and vector instruction load/store traffic

Four-entry vector touch queue (VTQ) supports all four architected AltiVec

data stream operations

Three-cycle GPR and AltiVec load latency (byte, half-word, word, vector)

with one-cycle throughput

Four-cycle FPR load latency (single, double) with one-cycle throughput

No additional delay for misaligned access within double-word boundary

Dedicated adder calculates effective addresses (EAs)

Supports store gathering

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