PC7447 datasheet(35/66 Pages) ATMEL

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PC7457/47 [Preliminary]

5345B–HIREL–02/04

IEEE 1149.1 AC Timing

Specifications

Table 15 provides the IEEE 1149.1 (JTAG) AC timing specifications as defined in Figure

19 through Figure 22 on page 37.

Notes:

1. All outputs are measured from the midpoint voltage of the falling/rising edge of TCLK to the midpoint of the signal in ques-

tion. The output timings are measured at the pins. All output timings assume a purely resistive 50

Ω load (see Figure 18).

Time-of-flight delays must be added for trace lengths, vias and connectors in the system.

2. TRST is an asynchronous level sensitive signal. The setup time is for test purposes only.

3. Non-JTAG signal input timing with respect to TCK.

4. Non-JTAG signal output timing with respect to TCK.

5. Guaranteed by design and characterization

Figure 18 provides the AC test load for TDO and the boundary-scan outputs of the PC7457.

Figure 18. Alternate AC Test Load for the JTAG Interface

Table 15. JTAG AC Timing Specifications (Independent of SYSCLK)

(1)at Recommended Operating Conditions

(see Table 3 on page 12)

Symbol

Parameter

Min

Max

Unit

fTCLK

TCK frequency of operation

33.3

MHz

TCLK

TCK cycle time

–

tJHJL

TCK clock pulse width measured at 1.4V

–

tJR and tJF

TCK rise and fall times

TRST

(2)

TRST assert time

–

DVJH

(3)

tIVJH

Input Setup Times:

Boundary-scan data

TMS, TDI

–

tDXJH

(3)

tIXJH

Input Hold Times:

Boundary-scan data

TMS, TDI

–

tJLDV

(4)

JLOV

Valid Times:

Boundary-scan data

TDO

JLDX

(4)

JLOX

Output hold times:

Boundary-scan data

TDO

TBD

JLDZ

(4)(5)

tJLOZ

TCK to output high impedance:

Boundary-scan data

TDO

Output

Z0 = 50Ω

RL = 50Ω

OVDD/2

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