PC7447 datasheet(42/66 Pages) ATMEL

42 / 66 page

PC7457/47 [Preliminary]

5345B–HIREL–02/04

Notes:

1. OVDD supplies power to the processor bus, JTAG, and all control signals; and VDD supplies power to the processor core and

the PLL (after filtering to become AV

DD). To program the I/O voltage, connect BVSEL to either GND (selects 1.8V) or to

HRESET (selects 2.5V). If used, the pull-down resistor should be less than 250

Ω. For actual recommended value of V

IN or

supply voltages see

Figure 3 on page 12.

2. Unused address pins must be pulled down to GND.

3. These pins require weak pull-up resistors (for example, 4.7 k

Ω) to maintain the control signals in the negated state after they

have been actively negated and released by the PC7447 and other bus masters.

4. This signal selects between MPX bus mode (asserted) and 60x bus mode (negated) and will be sampled at HRESET going

high.

5. This signal must be negated during reset, by pull up to OVDD or negation by ¬HRESET (inverse of HRESET), to ensure

proper operation.

6. Internal pull up on die.

7. Ignored in 60x bus mode.

8. These signals must be pulled down to GND if unused, or if the PC7447 is in 60x bus mode.

9. These input signals are for factory use only and must be pulled down to GND for normal machine operation.

10. It is recommended this test signal be tied to HRESET; however, other configurations will not adversely affect performance.

11. These signals are for factory use only and must be left unconnected for normal machine operation.

12. These input signals are for factory use only and must be pulled up to OVDD for normal machine operation.

13. This pin can externally cause a performance monitor event. Counting of the event is enabled via software.

14. This signal must be asserted during reset, by pull down to GND or assertion by HRESET, to ensure proper operation

PC7447 bảng dữ liệu(PDF) 42 Page - ATMEL Corporation