DLPC3470 datasheet(60/70 Pages) TI1

60 / 70 page

DLPC3470

DLPS110 – APRIL 2018

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Product Folder Links: DLPC3470

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Due to board variations, these are impossible to define. Any board designs should SPICE simulate with the ASIC IBIS models to ensure

single routing lengths do not exceed requirements.

11.1.5 Maximum Pin-to-Pin, PCB Interconnects Etch Lengths

Table 14. Max Pin-to-Pin PCB Interconnect Recommendations

DMD BUS SIGNAL

SIGNAL INTERCONNECT TOPOLOGY

UNIT

SINGLE BOARD SIGNAL ROUTING

LENGTH

MULTI-BOARD SIGNAL ROUTING

LENGTH

DMD_HS_CLK_P

DMD_HS_CLK_N

6.0

152.4

See

inch

(mm)

DMD_HS_WDATA_A_P

DMD_HS_WDATA_A_N

6.0

152.4

See

inch

(mm)

DMD_HS_WDATA_B_P

DMD_HS_WDATA_B_N

DMD_HS_WDATA_C_P

DMD_HS_WDATA_C_N

DMD_HS_WDATA_D_P

DMD_HS_WDATA_D_N

DMD_HS_WDATA_E_P

DMD_HS_WDATA_E_N

DMD_HS_WDATA_F_P

DMD_HS_WDATA_F_N

DMD_HS_WDATA_G_P

DMD_HS_WDATA_G_N

DMD_HS_WDATA_H_P

DMD_HS_WDATA_H_N

DMD_LS_CLK

6.5

165.1

See

inch

(mm)

DMD_LS_WDATA

6.5

165.1

See

inch

(mm)

DMD_LS_RDATA

6.5

165.1

See

inch

(mm)

DMD_DEN_ARSTZ

7.0

177.8

See (1)

inch

(mm)

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