DLPC3470 datasheet(54/70 Pages) TI1

54 / 70 page

VDD_PLLM/D (1.1 V)

VDD (1.1 V)

PARKZ

PLL_REFCLK

RESETZ

I2C (activity)

HOST_IRQ

500 ms Min

0 µs Min

0 µs

Max

VCC18 (1.8 V)

VDDLP12 (if not

tied to VDD)

Point at which all supplies reach 95% of

their specified nominal values.

PARKZ must be set high a minimum

of 0 µs before RESETZ is released to

support auto-initialization.

PLL_REFCLK may be active

before power is applied.

HOST_IRQ is driven high when

power and RESETZ are applied to

indicate the controller is not ready for

operation, and then is driven low after

initialization is complete.

PLL_REFCLK must become stable within

5 ms of all power being applied (for

external oscillator application this is

oscillator dependent and for crystal

applications this is crystal and ASIC

oscillator cell dependent).

I2C access can start immediately

after HOST_IRQ goes low (this

should occur within 500 ms from the

release of RESETZ).

PROJ_ON input

(GPIO_8)

0 µs

Min

0 µs

Min

5 ms Min

0 µs Min

HOST_IRQ is pulled high

immediately after RESETZ is

asserted low.

VCC_INTF (1.8 to 3.3 V)

VCC_FLSH (1.8 to 3.3 V)

500 µs

Min

PLL_REFCLK and all ASIC

supplies (except VDDLP12)

must remain active for a

minimum of 500 µs after

PROJ_ON goes low.

VCC18 must remain ON long

enough to satisfy DMD power

sequencing requirements

defined in the DLPA200x

specification.

I2C activity should cease

immediately upon

de-

assertion on PROJ_ON.

DLPC3470

DLPS110 – APRIL 2018

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Product Folder Links: DLPC3470

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System Power-Up and Power-Down Sequence (continued)

Figure 33. DLPC3470 controller Power-Up / PROJ_ON = 0 Initiated Normal PARK and Power-Down

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