DLPC3470 datasheet(26/70 Pages) TI1

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SPI_CLK

(ASIC Output)

SPI_DIN

(ASIC Inputs)

SPI_DOUT, SPI_CS(1:0)

(ASIC Outputs)

tp_h

tclkper

twh

twl

tp_su

tp_clqx

tp_clqv

DLPC3470

DLPS110 – APRIL 2018

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(1)

Standard SPI protocol is to transmit data on the falling edge of SPI_CLK and capture data on the rising edge. The DLPC3470 controller

does transmit data on the falling edge, but it also captures data on the falling edge rather than the rising edge. This provides support for

SPI devices with long clock-to-Q timing. DLPC3470 controller hold capture timing has been set to facilitate reliable operation with

standard external SPI protocol devices.

(2)

With the above output timing, DLPC3470 controller provides the external SPI device 8.2-ns input set-up and 8.2-ns input hold, relative to

the rising edge of SPI_CLK.

(3)

This range include the 200 ppm of the external oscillator (but no jitter).

6.15 Flash Interface Timing Requirements

The DLPC3470 controller ASIC flash memory interface consists of a SPI flash serial interface with a programmable clock

rate. The DLPC3470 controller can support 1- to 16-Mb flash memories.

(1) (2)

MIN

MAX

UNIT

fclock

Clock frequency, SPI_CLK

See (3)

1.42

36.0

MHz

tp_clkper

Clock period, SPI_CLK

50% reference points

704

27.7

tp_wh

Pulse duration low, SPI_CLK

50% reference points

352

tp_wl

Pulse duration high, SPI_CLK

50% reference points

352

Transition time – all signals

20% to 80% reference

points

0.2

3.0

tp_su

Setup time – SPI_DIN valid before SPI_CLK falling

edge

50% reference points

10.0

tp_h

Hold time – SPI_DIN valid after SPI_CLK falling edge

50% reference points

0.0

tp_clqv

SPI_CLK clock falling edge to output valid time –

SPI_DOUT and SPI_CSZ

50% reference points

1.0

tp_clqx

SPI_CLK clock falling edge output hold time –

SPI_DOUT and SPI_CSZ

50% reference points

–3.0

3.0

Figure 6. Flash Interface Timing

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