DLPC3470 datasheet(25/70 Pages) TI1

25 / 70 page

DLPC3470

www.ti.com

DLPS110 – APRIL 2018

Product Folder Links: DLPC3470

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(1)

The BT.656 interface accepts 8-bits per color, 4:2:2 YCb/Cr data encoded per the industry standard through PDATA(7:0) on the active

edge of PCLK (that is programmable). See .

(2)

Clock jitter should be calculated using this formula: Jitter = [1 / fclock – 5.76 ns]. Setup and hold times must be met during clock jitter.

6.14 BT656 Interface General Timing Requirements

The DLPC3470 controller ASIC input interface supports the industry standard BT.656 parallel video interface. See the

appropriate ITU-R BT.656 specification for detailed interface timing requirements.

(1)

MIN

MAX

UNIT

ƒclock

Clock frequency, PCLK

1.0

33.5

MHz

tp_clkper

Clock period, PCLK

50% reference points

29.85

1000

tp_clkjit

Clock jitter, PCLK

Max fclock

See (2)

tp_wh

Pulse duration low, PCLK

50% reference points

10.0

tp_wl

Pulse duration high, PCLK

50% reference points

10.0

tp_su

Setup time – PDATA(7:0) before the active edge of

PCLK

50% reference points

3.0

tp_h

Hold time – PDATA(7:0) after the active edge of

PCLK

50% reference points

0.9

Transition time – all signals

20% to 80% reference points

0.2

3.0

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