CCG3PA datasheet(5/37 Pages) CYPRESS

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Document Number: 002-16951 Rev. *F

Page 5 of 37

EZ-PD™ CCG3PA Datasheet

priate voltage on VBUS pin as per the negotiated contract with

the peer device over Type-C.

Integrated Digital Blocks

Serial Communication Blocks (SCB)

EZ-PD CCG3PA has two SCBs, which can be configured to

implement an I2C, SPI, or UART interface. The hardware I2C

blocks implement full multi-master and slave interfaces capable

of multimaster arbitration. In the SPI mode, the SCB blocks can

be configured to act as master or slave.

In the I2C mode, the SCB blocks are capable of operating at

speeds of up to 1 Mbps (Fast Mode Plus) and have flexible

buffering options to reduce interrupt overhead and latency for the

CPU. These blocks also support I2C that creates a mailbox

address range in the memory of EZ-PD CCG3PA and effectively

reduce I2C communication to reading from and writing to an

array in memory. In addition, the blocks support 8-deep FIFOs

for receive and transmit which, by increasing the time given for

the CPU to read data, greatly reduce the need for clock

stretching caused by the CPU not having read data on time.

The I2C peripherals are compatible with the I2C Standard-mode,

Fast-mode, and Fast-mode Plus devices as defined in the NXP

I2C-bus specification and user manual (UM10204). The I2C bus

I/Os are implemented with GPIO in open-drain modes.

The I2C port on the SCB blocks of EZ-PD CCG3PA are not

completely compliant with the I2C spec in the following aspects:

■ The GPIO cells for SCB 1’s I2C port are not overvoltage-tolerant

and, therefore, cannot be hot-swapped or powered up

independently of the rest of the I2C system.

■ Fast-mode Plus has an IOL specification of 20 mA at a VOL of

0.4 V. The GPIO cells can sink a maximum of 8-mA IOL with a

VOL maximum of 0.6 V.

■ Fast-mode and Fast-mode Plus specify minimum Fall times,

which are not met with the GPIO cell; Slow strong mode can

help meet this spec depending on the bus load.

Timer/Counter/PWM Block (TCPWM)

EZ-PD CCG3PA has four TCPWM blocks. Each implements a

16-bit timer, counter, pulse-width modulator (PWM), and

quadrature decoder functionality. The block can be used to

measure the period and pulse width of an input signal (timer),

find the number of times a particular event occurs (counter),

generate PWM signals, or decode quadrature signals.

I/O Subsystem

EZ-PD CCG3PA has up to 12 GPIOs of which, some of them can

be re-purposed to support functions of SCB (I2C, UART, SPI).

GPIO pins P0.0 and P0.1 are overvoltage-tolerant (OVT) (upto

7V).

The GPIO block implements the following:

■ Seven drive strength modes:

❐ Input only

❐ Weak pull-up with strong pull-down

❐ Strong pull-up with weak pull-down

❐ Open drain with strong pull-down

❐ Open drain with strong pull-up

❐ Strong pull-up with strong pull-down

❐ Weak pull-up with weak pull-down

■ Input threshold select (CMOS or LVTTL)

■ Individual control of input and output buffer enabling/disabling

in addition to the drive strength modes

■ Hold mode for latching previous state (used for retaining I/O

state in Deep Sleep mode)

■ Selectable slew rates for dV/dt related noise control to improve

EMI

During power-on and reset, the I/O pins are forced to the disable

state so as not to crowbar any inputs and/or cause excess

turn-on current. A multiplexing network known as a high-speed

I/O matrix is used to multiplex between various signals that may

connect to an I/O pin.

Port pins P1.0 and P1.1 can be configured to indicate Fault for

OCP/SCP/OVP/UVP conditions. Any two fault conditions can be

mapped to two GPIOs or all the four faults can be OR’ed to

indicate over one GPIO.

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