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HT67F5652 bảng dữ liệu(PDF) 154 Page - Holtek Semiconductor Inc |
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HT67F5652 bảng dữ liệu(HTML) 154 Page - Holtek Semiconductor Inc |
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154 / 224 page ![]() Rev. 1.00 154 De�e��e� 0�� �01� Rev. 1.00 155 De�e��e� 0�� �01� HT67F5652 24-Bit Delta Sigma A/D + LCD Flash MCU HT67F5652 24-Bit Delta Sigma A/D + LCD Flash MCU UART Data Transfer Scheme TheblockdiagramshowstheoveralldatatransferstructurearrangementfortheUART.Theactual datatobetransmittedfromtheMCUisfirsttransferredtotheTXR_RXRregisterbytheapplication program.ThedatawillthenbetransferredtotheTransmitShiftRegisterfromwhereitwillbe shiftedout,LSBfirst,ontotheTXpinataratecontrolledbytheBaudRateGenerator.Onlythe TXR_RXRregisterismappedontotheMCUDataMemory,theTransmitShiftRegisterisnot mappedandisthereforeinaccessibletotheapplicationprogram. DatatobereceivedbytheUARTisacceptedontheexternalRXpin,fromwhereitisshiftedin, LSBfirst,totheReceiverShiftRegisterataratecontrolledbytheBaudRateGenerator.Whenthe shiftregisterisfull,thedatawillthenbetransferredfromtheshiftregistertotheinternalTXR_RXR register,whereitisbufferedandcanbemanipulatedbytheapplicationprogram.OnlytheTXR_ RXRregisterismappedontotheMCUDataMemory,theReceiverShiftRegisterisnotmappedand isthereforeinaccessibletotheapplicationprogram. Itshouldbenotedthattheactualregisterfordatatransmissionandreception,althoughreferredto inthetext,onlyexistsasasinglesharedregisterintheDataMemory.Thissharedregisterknownas theTXR_RXRregisterisusedforbothdatatransmissionanddatareception. MSB LSB ………………………… T�ans�itte� Shift Registe� (TSR) MSB LSB ………………………… Re�eive� Shift Registe� (RSR) TX Pin RX Pin Baud Rate Gene�ato� TXR_RXR Registe� TXR_RXR Registe� Data to �e t�ans�itted Data �e�eived Buffe� fSYS MCU Data Bus UART Data Transfer Scheme UART Status and Control Registers TherearefivecontrolregistersassociatedwiththeUARTfunction.TheUSR,UCR1andUCR2 registerscontroltheoverallfunctionoftheUART,whiletheBRGregistercontrolstheBaudrate. TheactualdatatobetransmittedandreceivedontheserialinterfaceismanagedthroughtheTXR_ RXRdataregister. Register Name Bit 7 6 5 4 3 2 1 0 USR PERR NF FERR OERR RIDLE RXIF TIDLE TXIF UCR1 UARTEN BNO PREN PRT STOPS TXBRK RX8 TX8 UCR� TXEN RXEN BRGH ADDEN WAKE RIE TIIE TEIE TXR_ RXR TXRX� TXRX� TXRX5 TXRX4 TXRX3 TXRX� TXRX1 TXRX0 BRG BRG� BRG� BRG5 BRG4 BRG3 BRG� BRG1 BRG0 UART Register Summary |
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