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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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HT67F5652 bảng dữ liệu(PDF) 127 Page - Holtek Semiconductor Inc |
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HT67F5652 bảng dữ liệu(HTML) 127 Page - Holtek Semiconductor Inc |
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127 / 224 page  Rev. 1.00 1�� De�e��e� 0�� �01� Rev. 1.00 1�� De�e��e� 0�� �01� HT67F5652 24-Bit Delta Sigma A/D + LCD Flash MCU HT67F5652 24-Bit Delta Sigma A/D + LCD Flash MCU • ADCR1 Register Bit 7 6 5 4 3 2 1 0 Na�e FLMS� FLMS1 FLMS0 VRBUFN VRBUFP ADCDL EOC — R/W R/W R/W R/W R/W R/W R/W R/W — POR 0 0 0 0 0 0 0 — Bit7~5 FLMS2~FLMS0:A/Dconverterclockdividedratioselectionandsampleddata doublingfunction(CHOP)enablecontrol 000:CHOP=2,fADCK=fMCLK/30 010:CHOP=2,fADCK=fMCLK/12 100:CHOP=1,fADCK=fMCLK/30 110:CHOP=1,fADCK=fMCLK/12 Others:Reserved WhentheCHOPbitisequalto2,itmeansthatthesampleddataamountwillbe doubledforthenormalconversionmode.However,itcanberegardedasthelow latencyconversionmodeiftheCHOPbitisequalto1,whichmeansthatthesampled datadoublingfunctionisdisabled. Bit4 VRBUFN:A/Dconverternegativereferencevoltageinput(VRN)buffercontrol 0:Disableinputbufferandenablebypassfunction 1:Enableinputbufferanddisablebypassfunction Bit3 VRBUFP:A/Dconverterpositivereferencevoltageinput(VRP)buffercontrol 0:Disableinputbufferandenablebypassfunction 1:Enableinputbufferanddisablebypassfunction Bit2 ADCDL:A/Dconverteddatalatchfunctionenablecontrol 0:Disabledatalatchfunction 1:Enabledatalatchfunction IftheA/Dconverteddatalatchfunctionisenabled,thelatestconverteddatavaluewill belatchedandnotbeupdatedbyanysubsequentconvertedresultsuntilthisfunction isdisabled.Althoughtheconverteddataislatchedintothedataregisters,theA/D convertercircuitsremainoperational,butwillnotgenerateinterruptandEOCwillnot change.Itisrecommendedthatthisbitshouldbesethighbeforereadingtheconverted dataintheADRL,ADRMandADRHregisters.Aftertheconverteddatahasbeen readout,thebitcanthenbeclearedtolowtodisabletheA/Dconverterdatalatch functionandallowfurtherconversionvaluestobestored.Inthisway,thepossibility ofobtainingundesireddataduringA/Dconverterconversionscanbeprevented. Bit1 EOC:EndofA/Dconversionflag 0:A/Dconversioninprogress 1:A/Dconversionended Thisbitmustbeclearedbysoftware. Bit0 Unimplemented,readas"0" • ADCS Register Bit 7 6 5 4 3 2 1 0 Na�e — — — ADCK4 ADCK3 ADCK� ADCK1 ADCK0 R/W — — — R/W R/W R/W R/W R/W POR — — — 0 0 0 0 0 Bit7~5 Unimplemented,readas"0" Bit4~0 ADCK4~ADCK0:A/DconverterclocksourcefMCLKdividedratioselection 00000~11110:fMCLK=fSYS/2/(ADCK[4:0]+1) 11111:fMCLK=fSYS |
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