ATPL00B datasheet(40/152 Pages) ATMEL

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Atmel ATPL00B [datasheet]

43028A-ATPL - 9/12

4.5.2

Power Saving Modes

ADD8051C3A has two power-saving modes, Idle and Power Down.

In the Idle mode (IDL = 1), the CPU is stopped but the peripheral circuits continue running.

In Power Down (PD = 1), the CPU and the peripheral circuits are stopped, except external interrupts hardware that can

be configured to run when in power down mode.

The Idle and Power Down Modes are activated by setting bits in Special Function Register PCON. If 1s are written to

PD and IDL at the same time, PD takes precedence. When watchdog is enabled power down modes are automatically

disabled.

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

B it 0

PCON

SMOD

WLE

GF1

GF0

IDL



SMOD: Double baud rate bit when timer 1 is used as time generator and serial port is in

modes 1, 2 or 3



--: Reserved bits



WLE: Watchdog load enable. It must be set by software to enable T3 reload. It is reset by

hardware after 13 machine cycles



GF1: General purpose flag bit, user programmable



GF0: General purpose flag bit, user programmable



PD: Sets power-down mode



IDL: Sets idle mode

4.5.3

Idle Mode

Setting PCON(0), CPU is stopped but peripheral circuits (Interrupts, Timers, Standard Serial Interface and Serial

Peripheral Interface functions) continue running. The CPU status is entirely preserved; Stack Pointer, Program Counter,

Program Status Word, Accumulator, and all other registers maintain their data during Idle. The port pins hold the logical

states they had at the time Idle was activated. PSEN holds at logic high level.

There are two ways to terminate the Idle mode.

Activation of any enabled interrupt will cause PCON(0) to be cleared by hardware, terminating the Idle mode.

The interrupt will be served, and following RETI, the next instruction to be executed will be the one following

the instruction that put the device into Idle.

Reset signal. The signal at the RSTA pin redefines all the SFR values to their reset values and then the IDL bit

is cleared. At this time, and with three clock cycle delay, the CPU restart program execution with program

counter at initial value 0x0000, RAM content remains unchanged.

4.5.4

Power-Down Mode

An instruction that sets PCON(1) causes that to be the last instruction executed before going into the Power Down

mode. In the Power Down mode all functions are stopped, except external interrupts hardware. The contents of the on-

chip RAM and Special Function Registers are maintained. The port pins output the values held by their respective

SFRs. The PSEN output is held low.

There are two ways to exit Power Down mode.

Hardware reset. Hardware reset redefines all the SFRs.

External interrupt. External interrupts must be configured for low level activation.When they are enabled a low

level at their inputs will cause a microcontroller restart and a jump to the corresponding interruption routine. As

in idle mode, the interrupt will be served, and following RETI, the next instruction to be executed will be the

one following the instruction that put the device into power down.

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