ATPL00B datasheet(97/152 Pages) ATMEL

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Atmel ATPL00B [datasheet]

43028A-ATPL - 9/12

10.3.2 FLAGS1 register

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

B it 0

FLAGS1

BYP

ZER0_A

NMDR

RxFEC

Name:

FLAGS1

Address:

0xFE01

Reset:

“00010000”

This register holds a mode operation bit, some special purpose bits and the RX and TX flags to control the transmission

and reception processes. The MCU has full access to this register.

--:

Reserved bit

BYP:

Bypass mode

When this mode is enabled, the MAC logic is disabled and the MCU takes full control of the

PLC modem



„0‟: Bypass mode disabled



„1‟: Bypass mode enabled

ZER0_A:

Errors allowed in preamble

This field selects whether erroneous bits are allowed in preamble reception or not



„0‟: No errors are allowed in preamble reception. A(1:0) field (see CTRL register in 10.3.1)

sets the number of

0xA‟s expected to be received. If there is any erroneous bit in this

preamble reception, the frame will be discarded.



„1‟: Errors are allowed in preamble reception. The frame will be discarded only if the

erroneous bits received in preamble exceed a threshold (see TH_PREAM register in

10.3.5).

NMDR:

No more data required

This bit should be set by the MCU after the last byte of the payload is being sent or received

through the DATA register. In FCS mode it would mean that the next field to be processed by

the MAC is the FCS field.

Setting the NMDR bit is only required in the following situations:

a) Message transmissions with TX interrupt enabled.

b) Message receptions in FCS mode with Viterbi algorithm disabled.



„0‟: NMDR deasserted



„1‟: NMDR asserted

RxFEC:

Receive FEC fields

If this bit is set, FEC fields are also delivered by the MAC to the MCU by means of DATA

are made accessible to the MCU.



„0‟: Only data bytes are read by the MCU



‟1‟: Both data and FEC are read by the MCU

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