ACEX1 datasheet(57/86 Pages) ETC

57 / 86 page

Altera Corporation

ACEX 1K Programmable Logic Device Family Data Sheet

Table 25. EAB Timing Macroparameters

Notes (1), (6)

Symbol

Parameter

Conditions

tEABAA

EAB address access delay

tEABRCCOMB

EAB asynchronous read cycle time

tEABRCREG

EAB synchronous read cycle time

tEABWP

EAB write pulse width

tEABWCCOMB

EAB asynchronous write cycle time

tEABWCREG

EAB synchronous write cycle time

tEABDD

EAB data-in to data-out valid delay

tEABDATACO

EAB clock-to-output delay when using output registers

tEABDATASU

EAB data/address setup time before clock when using input register

tEABDATAH

EAB data/address hold time after clock when using input register

tEABWESU

EAB WE setup time before clock when using input register

tEABWEH

EAB WE hold time after clock when using input register

tEABWDSU

EAB data setup time before falling edge of write pulse when not using input

registers

tEABWDH

EAB data hold time after falling edge of write pulse when not using input

registers

tEABWASU

EAB address setup time before rising edge of write pulse when not using

input registers

tEABWAH

EAB address hold time after falling edge of write pulse when not using input

registers

tEABWO

EAB write enable to data output valid delay

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