ACEX1 datasheet(37/86 Pages) ETC

37 / 86 page

Altera Corporation

ACEX 1K Programmable Logic Device Family Data Sheet

For designs that require both a multiplied and non-multiplied clock, the

clock trace on the board can be connected to the GCLK1 pin. In the Altera

software, the GCLK1 pin can feed both the ClockLock and ClockBoost

circuitry in the ACEX 1K device. However, when both circuits are used,

the other clock pin cannot be used.

ClockLock & ClockBoost Timing Parameters

For the ClockLock and ClockBoost circuitry to function properly, the

incoming clock must meet certain requirements. If these specifications are

not met, the circuitry may not lock onto the incoming clock, which

generates an erroneous clock within the device. The clock generated by

the ClockLock and ClockBoost circuitry must also meet certain

specifications. If the incoming clock meets these requirements during

configuration, the ClockLock and ClockBoost circuitry will lock onto the

clock during configuration. The circuit will be ready for use immediately

after configuration. Figure 19 shows the incoming and generated clock

specifications.

Figure 19. Speciﬁcations for the Incoming & Generated Clocks

Note (1)

Note:

(1)

The tI parameter refers to the nominal input clock period; the tO parameter refers to the nominal output clock

period.

Input

Clock

ClockLock

Generated

Clock

tCLK1

tINDUTY

tI+ tCLKDEV

tI+ tINCLKSTB

tO tJITTER

tO+ tJITTER

tOUTDUTY

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