ACEX1 datasheet(50/86 Pages) ETC

50 / 86 page

Altera Corporation

ACEX 1K Programmable Logic Device Family Data Sheet

Figure 23. Output Drive Characteristics of ACEX 1K Devices

Timing Model

The continuous, high-performance FastTrack Interconnect routing

resources ensure accurate simulation and timing analysis as well as

predictable performance. This predictable performance contrasts with

that of FPGAs, which use a segmented connection scheme and, therefore,

have an unpredictable performance.

Device performance can be estimated by following the signal path from a

source, through the interconnect, to the destination. For example, the

registered performance between two LEs on the same row can be

calculated by adding the following parameters:

LE register clock-to-output delay (tCO)

Interconnect delay (tSAMEROW)

LE look-up table delay (tLUT)

LE register setup time (tSU)

The routing delay depends on the placement of the source and destination

LEs. A more complex registered path may involve multiple combinatorial

LEs between the source and destination LEs.

Timing simulation and delay prediction are available with the simulator

and Timing Analyzer, or with industry-standard EDA tools. The

Simulator offers both pre-synthesis functional simulation to evaluate logic

design accuracy and post-synthesis timing simulation with 0.1-ns

resolution. The Timing Analyzer provides point-to-point timing delay

information, setup and hold time analysis, and device-wide performance

analysis.

VO Output Voltage (V)

IOL

IOH

VCCINT = 2.5

VCCIO = 2.5

Room Temperature

VCCINT = 2.5

VCCIO = 3.3

Room Temperature

VO Output Voltage (V)

IOL

Typical I

Output

Current (mA)

Typical I

Output

Current (mA)

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