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PC87372 bảng dữ liệu(PDF) 68 Page - National Semiconductor (TI) |
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PC87372 bảng dữ liệu(HTML) 68 Page - National Semiconductor (TI) |
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68 / 144 page ![]() 5.0 General-Purpose Input/Output (GPIO) Ports (Continued) 68 www.national.com Revision 1.2 5.4.3 GPIO Data Out Register (GPDO) Power Well: VSB3 Location: Device specific Type: R/W or RO 5.4.4 GPIO Data In Register (GPDI) Power Well: VSB3 Location: Device specific Type: RO Bit 76543210 Name DATAOUT Reset 11111111 Bit Description 7-0 DATAOUT (Data Out). Bits 7-0 correspond to pins 7-0 of the specific Port. The value of each bit determines the value driven on the corresponding GPIO pin when its output buffer is enabled. Writing to the bit latches the written data unless the bit is locked by the GPCFG register Lock bit. Reading the bit returns its value regardless of the pin value and configuration. 0: Corresponding pin driven to low 1: Corresponding pin driven or released (according to buffer type selection) to high (default) Bit 76543210 Name DATAIN Reset XXXXXXXX Bit Description 7-0 DATAIN (Data In). Bits 7-0 correspond to pins 7-0 of the specific Port. Reading each bit returns the value of the corresponding GPIO pin. Pin configuration and the GPDO register value may influence the pin value. Write is ignored. 0: Corresponding pin level low 1: Corresponding pin level high |
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