PC87372 datasheet(61/144 Pages) NSC

61 / 144 page

3.0 Device Architecture and Configuration (Continued)

www.national.com

Revision 1.2

3.14.3 Fan Speed Monitor Configuration Register (FSMCF)

This register is reset to 00h.

Power Well: VDD3

Location:

Index F0h

Type:

Varies per bit

Bit

76543210

Name

LOCKFCF

Reserved

FANMON

_EN2

Reserved

FANMON

_EN1

Reserved

Reset

00000000

Bit

Type

Description

R/W1S LOCKFCF (Lock Fan Speed Configuration). When set to 1, this bit locks the bits of the FSMCF

by VDD3 Power-Up reset (or Hardware reset).

0: R/W bits are enabled for write (default)

1: All bits are RO

6-5

−

Reserved.

R/W or

FANMON_EN2 (Fan Monitor Enable 2). When this bit is set to 1, the Fan Speed Monitor 2 is enabled

and the rate of pulses received at the FANTACH2 tachometer input is measured.

0: Disabled (default)

1: Enabled

3-2

−

Reserved.

R/W or

FANMON_EN1 (Fan Monitor Enable 1). When this bit is set to 1, the Fan Speed Monitor 1 is enabled

and the rate of pulses received at the FANTACH1 tachometer input is measured.

0: Disabled (default)

1: Enabled

−

Reserved.

PC87372 bảng dữ liệu(PDF) 61 Page - National Semiconductor (TI)

PC87372 bảng dữ liệu(HTML) 61 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL