PC87372 datasheet(47/144 Pages) NSC

47 / 144 page

3.0 Device Architecture and Configuration (Continued)

www.national.com

Revision 1.2

3.9 PARALLEL PORT (PP) CONFIGURATION

3.9.1

General Description

The PC87372 Parallel Port supports all IEEE1284 standard communication modes: Compatibility (also known as Standard

or SPP), Bi-directional (known also as PS/2), FIFO, EPP (also known as mode 4) and ECP (with an optional Extended ECP

mode).

The Parallel Port includes two groups of runtime registers (see Section 9.2 on page 112):

• A group of 21 registers at first level offset, sharing 14 entries. Three of these registers (at offsets 403h, 404h and 405h)

are used only in Extended ECP mode.

• A group of four registers, used only in Extended ECP mode, is accessed by a second level offset.

The desired mode is selected by the ECR runtime register (offset 402h). The selected mode determines which runtime reg-

isters are used and which address bits are used for the base address. The Parallel Port functional block registers are shown

in Section 9.2 on page 112. All of these registers are VDD3 powered.

3.9.2

Logical Device 1 (PP) Configuration

Table 17 lists the configuration registers that affect the Parallel Port. Only the last register (F0h) is described here. See Sec-

tion 3.2.3 on page 32 for descriptions of the other configuration registers. All of these registers are VDD3 powered.

Table 17. Parallel Port Conﬁguration Registers

Index

Conﬁguration Register or Action

Type

Power Well

Reset

30h Activate (see Section 3.3.1 on page 36)

R/W

VDD3

00h

60h Base Address MSB register. Bits 7-3 (for A15-11) are read only, ‘00000’. Bit 2

(for A10) must be ‘0’.

R/W

VDD3

02h

61h Base Address LSB register. Bits 1 and 0 (A1 and A0) are read only, ‘00’. For ECP

mode 4 (EPP) or when using Extended registers, bit 2 (A2) must also be ‘0’.

R/W

VDD3

78h

70h Interrupt Number and Wake-Up on IRQ Enable register

R/W

VDD3

07h

71h Interrupt Type:

- Bits 7-2 are read only.

- Bit 1 is a read/write bit.

- Bit 0 is read only. It reﬂects the interrupt type dictated by the Parallel Port

operation mode. This bit is set to 1 (level interrupt) in Extended mode and

cleared (edge interrupt) in all other modes.

R/W

VDD3

02h

74h DMA Channel Select

R/W

VDD3

04h

75h Report no second DMA assignment

VDD3

04h

F0h Parallel Port Standard Conﬁguration register

R/W

VDD3

F2h

F8h Parallel Port Modiﬁed Conﬁguration register

R/W

VDD3

07h

PC87372 bảng dữ liệu(PDF) 47 Page - National Semiconductor (TI)

PC87372 bảng dữ liệu(HTML) 47 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL