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PC87372 bảng dữ liệu(PDF) 43 Page - National Semiconductor (TI) |
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PC87372 bảng dữ liệu(HTML) 43 Page - National Semiconductor (TI) |
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43 / 144 page ![]() 3.0 Device Architecture and Configuration (Continued) 43 www.national.com Revision 1.2 3.7.6 Clock Generator Control Register (CLOCKCF) Power Well: VSB3 Location: Index 29h Type: Varies per bit Bit 76 5 43210 Name HFCGEN Reserved CKVALID Reserved Reset 0 0 0 00000 Bit Type Description 7 R/W1S HFCGEN (Clock Generator Enable). When set to 1, this bit enables the operation of the Clock Generator, and locks the configuration register CLOCKCF by disabling writing to all its bits (including to the HFCGEN bit itself). Once set, this bit can be cleared by VDD3 Power-Up reset (or Hardware reset). 0: Clock Generator disabled; the R/W bits are enabled for write (default). 1: Clock Generator enabled; all the bits are RO. 6-5 − Reserved. 4RO CKVALID (Valid Clock Generator, Clock Status). This bit indicates the status of the on-chip, 48 MHz Clock Generator and controls the generator output clock signal. The PC87372 modules using this clock may be enabled (see Section 3.3.1 on page 36) only after this bit is read high (generator clock is valid). 0: Generator output clock frozen (default) 1: Generator output clock active (stable and toggling) 3-0 − Reserved. |
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