PC87372 datasheet(25/144 Pages) NSC

25 / 144 page

2.0 Power, Reset and Clocks (Continued)

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Revision 1.2

Figure 1 shows the power state transitions:

2.1.3

Power Connection and Layout Guidelines

The PC87372 requires a power supply voltage of 3.3V

± 10% for both the V

DD3 and VSB3 supplies. The on-chip Core power

converter generates a voltage below 3V for the internal logic.

VDD3, VSB3 and VCORF use a common ground return marked VSS.

To obtain the best performance, bear in mind the following recommendations.

Ground Connection. The following items must be connected to the ground layer (VSS) as close to the device as possible:

• The ground return (V

SS) pins

• The decoupling capacitors of the Main power supply (V

DD3) pins

• The decoupling capacitors of the Standby power supply (V

SB3) pins

• The decoupling capacitor of the Standby 5V supply (V

SB5) pin

• The decoupling capacitor of the on-chip Core power converter (V

CORF) pin

Note that a low-impedance ground layer also improves noise isolation.

Decoupling Capacitors. The following decoupling capacitors must be used in order to reduce EMI and ground bounce:

• Main power supply (V

DD3): Place one capacitor of 0.1 µF on each VDD3-VSS pin pair as close to the pin as possible. In

addition, place one 10

−47 µF tantalum capacitor on the common net as close to the chip as possible.

• Standby power supply (V

SB3): Place one capacitor of 0.1 µF on each VSB3-VSS pin pair as close to the pin as possible.

In addition, place one 10

−47 µF tantalum capacitor on the common net as close to the chip as possible.

• Standby 5V supply (V

SB5): Place one capacitor of 0.1 µF on the VSB5-VSS pin pair as close to the pin as possible.

• On-chip Core power converter (V

CORF): Place one 1 µF ceramic capacitor on the VCORF-VSS pin pair as close to the pin

as possible.

VDD3, VSB3 and VCORF Off

Power Fail

VDD3 Off, VSB3 and VCORF On

Power Off

VDD3, VSB3 and VCORF On

Power On

VSB3 On,

VDD3 On,

VSB3 Off

VDD3 Off

VDD3 On

VSB Power-Up Reset

VDD Power-Up Reset

VSB3 Off

VDD3 Off

Figure 1. Power State Transitions

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