TMS320DM6431 datasheet(129/227 Pages) TI1

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TMS320DM6431

Digital Media Processor

www.ti.com

SPRS342C – NOVEMBER 2006 – REVISED JUNE 2008

Table 6-6. DM6431 EDMA Channel Synchronization Events (continued)

EDMA

EVENT NAME

EVENT DESCRIPTION

CHANNEL

AREVTE0

McASP0 Receive Event Even

AREVTO0

McASP0 Receive Event Odd

AREVT0

McASP0 Receive Event

16-21

–

Reserved

URXEVT0

UART 0 Receive Event

UTXEVT0

UART 0 Transmit Event

–

Reserved

–

Reserved

–

Reserved

–

Reserved

ICREVT

I2C Receive Event

ICXEVT

I2C Transmit Event

30-31

–

Reserved

GPINT0

GPIO 0 Interrupt

GPINT1

GPIO 1 Interrupt

GPINT2

GPIO 2 Interrupt

GPINT3

GPIO 3 Interrupt

GPINT4

GPIO 4 Interrupt

GPINT5

GPIO 5 Interrupt

GPINT6

GPIO 6 Interrupt

GPINT7

GPIO 7 Interrupt

GPBNKINT0

GPIO Bank 0 Interrupt

GPBNKINT1

GPIO Bank 1 Interrupt

GPBNKINT2

GPIO Bank 2 Interrupt

GPBNKINT3

GPIO Bank 3 Interrupt

GPBNKINT4

GPIO Bank 4 Interrupt

GPBNKINT5

GPIO Bank 5 Interrupt

GPBNKINT6

GPIO Bank 6 Interrupt

–

Reserved

TEVTL0

Timer 0 Event Low Interrupt

TEVTH0

Timer 0 Event High Interrupt

TEVTL1

Timer 1 Event Low Interrupt

TEVTH1

Timer 1 Evemt High Interrupt

PWM0

PWM 0 Event

PWM1

PWM 1 Event

PWM2

PWM 2 Event

55-63

–

Reserved

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