TMS320DM6431 datasheet(128/227 Pages) TI1

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6.4 Enhanced Direct Memory Access (EDMA3) Controller

6.4.1

EDMA3 Channel Synchronization Events

TMS320DM6431

Digital Media Processor

SPRS342C – NOVEMBER 2006 – REVISED JUNE 2008

www.ti.com

The EDMA controller handles all data transfers between memories and the device slave peripherals on

the DM6431 device. These data transfers include cache servicing, non-cacheable memory accesses,

user-programmed data transfers, and host accesses. These are summarized as follows:

• Transfer to/from on-chip memories

–

DSP L1D memory

–

DSP L2 memory

• Transfer to/from external storage

–

DDR2 SDRAM

–

NAND flash

–

Asynchronous EMIF (EMIFA)

• Transfer to/from peripherals/hosts

–

McBSP0

–

McASP0

–

PWM

–

UART0

–

HECC

The EDMA supports two addressing modes: constant addressing and increment addressing. On the

DM6431, constant addressing mode is not supported by any peripheral or internal memory. For more

information on these two addressing modes, see the TMS320DM643x DMP Enhanced Direct Memory

Access (EDMA3) Controller User’s Guide (literature number SPRU987).

The EDMA supports up to 64 EDMA channels which service peripheral devices and external memory.

Table 6-6 lists the source of EDMA synchronization events associated with each of the programmable

EDMA channels. For the DM6431 device, the association of an event to a channel is fixed; each of the

EDMA channels has one specific event associated with it. These specific events are captured in the

EDMA event registers (ER, ERH) even if the events are disabled by the EDMA event enable registers

(EER, EERH). For more detailed information on the EDMA module and how EDMA events are enabled,

captured, processed, linked, chained, and cleared, etc., see the TMS320DM643x DMP Enhanced Direct

Memory Access (EDMA3) Controller User’s Guide (literature number SPRU987).

Table 6-6. DM6431 EDMA Channel Synchronization Events(1)

EDMA

EVENT NAME

EVENT DESCRIPTION

CHANNEL

0-1

–

Reserved

XEVT0

McBSP0 Transmit Event

REVT0

McBSP0 Receive Event

–

Reserved

–

Reserved

–

Reserved

–

Reserved

–

Reserved

–

Reserved

AXEVTE0

McASP0 Transmit Event Even

AXEVTO0

McASP0 Transmit Event Odd

AXEVT0

McASP0 Transmit Event

(1)

In addition to the events shown in this table, each of the 64 channels can also be synchronized with the transfer completion or alternate

transfer completion events. For more detailed information on EDMA event-transfer chaining, see the Document Support section for the

Enhanced Direct Memory Access (EDMA) Controller Reference Guide.

Peripheral Information and Electrical Specifications

128

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