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TMS320DM6431 bảng dữ liệu(PDF) 161 Page - Texas Instruments

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tên linh kiện TMS320DM6431
Giải thích chi tiết về linh kiện  Digital Media Processor
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TMS320DM6431 bảng dữ liệu(HTML) 161 Page - Texas Instruments

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6.9.3
EMIFA Electrical Data/Timing
TMS320DM6431
Digital Media Processor
www.ti.com
SPRS342C – NOVEMBER 2006 – REVISED JUNE 2008
Table 6-24. Timing Requirements for Asynchronous Memory Cycles for EMIFA Module(1)
(see Figure 6-14 and Figure 6-15)
-3/-3Q/-3S
NO.
UNIT
MIN
NOM
MAX
READS and WRITES
2
tw(EM_WAIT)
Pulse duration, EM_WAIT assertion and deassertion
2E
ns
READS
12
tsu(EMDV-EMOEH)
Setup time, EM_D[7:0] valid before EM_OE high
5
ns
13
th(EMOEH-EMDIV)
Hold time, EM_D[7:0] valid after EM_OE high
0
ns
tsu(EMWAIT-
14
Setup time, EM_WAIT asserted before EM_OE high(2)
4E + 5
ns
EMOEH)
WRITES
tsu(EMWAIT-
28
Setup time, EM_WAIT asserted before EM_WE high(2)
4E + 5
ns
EMWEH)
(1)
E = SYSCLK3 period in ns for EMIFA. For example, when running the DSP CPU at 300 MHz, use E = 20 ns.
(2)
Setup before end of STROBE phase (if no extended wait states are inserted) by which EM_WAIT must be asserted to add extended
wait states. Figure 6-16 and Figure 6-17 describe EMIF transactions that include extended wait states inserted during the STROBE
phase. However, cycles inserted as part of this extended wait period should not be counted; the 4E requirement is to the start of where
the HOLD phase would begin if there were no extended wait cycles.
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Peripheral Information and Electrical Specifications
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