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STW81200 bảng dữ liệu(PDF) 33 Page - STMicroelectronics

tên linh kiện STW81200
Giải thích chi tiết về linh kiện  Wideband RF PLL fractional/integer frequency synthesizer with integrated VCOs and LDOs
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STW81200 bảng dữ liệu(HTML) 33 Page - STMicroelectronics

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STW81200
Circuit description
57
The Data bits are stored in the internal shift register on the rising edge of SCK.
The first bit, CO is used for mode selection (0=Write Operation, 1=Read Operation). The bit
A[3:0] represents the register address, and D[26:0] are the data bits.
In some registers, the first data bit D26 is used (when set to ‘1’) for double-buffering
purposes. In this case the register content is stored in a temporary buffer and is transferred
to the internal register once a write operation is done on the master register ST0.
Figure 32. SPI timing diagram
Table 10. SPI timings
Parameter
Comments
Min
Typ
Max
Unit
Tsetup
data to clock setup time
4-
-
ns
Thold
data to clock hold time
1-
-
ns
Tck
clock cycle period
20
-
-
ns
Tdi
disable pulse width
4-
-
ns
Tcd
clock-to-disable time
1-
-
ns
Tec
enable-to-clock time
3-
-
ns



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